How APIC Task Priority Register works

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mrjbom
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How APIC Task Priority Register works

Post by mrjbom »

I am implementing an APIC timer and wiki says I should “Make sure the TPR (Task Priority Register) is set (so it won't block/postpone lower priority IRQs)”, I tried to find a description of TPR in Intel Manual but I was not able to do so(I would be glad if you could show me the location in the latest SDM).

I don't quite understand what value should be set for TPR, by default it is set to 0.
Also, I don't quite understand where the interrupt priority is specified, I guess it depends on the interrupt vector, the larger the vector the lower the priority, right?
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Octocontrabass
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Re: How APIC Task Priority Register works

Post by Octocontrabass »

mrjbom wrote: ↑Tue Dec 10, 2024 5:52 pmI tried to find a description of TPR in Intel Manual but I was not able to do so(I would be glad if you could show me the location in the latest SDM).
Volume 3A section 12.8.3 explains how the Task Priority Register works. Volume 3A section 12.8.6 explains the different ways you can access the TPR.
mrjbom wrote: ↑Tue Dec 10, 2024 5:52 pmI don't quite understand what value should be set for TPR, by default it is set to 0.
You should set the TPR to 0 if you aren't using it.
mrjbom wrote: ↑Tue Dec 10, 2024 5:52 pmAlso, I don't quite understand where the interrupt priority is specified, I guess it depends on the interrupt vector, the larger the vector the lower the priority, right?
Larger vectors have higher priority, not lower priority.
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