Intel Atom Elkhart Lake APIC Timer

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ravi
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Intel Atom Elkhart Lake APIC Timer

Post by ravi »

Hello Octocontrabass

as per the information i have read APIC timer ticks of the CPU clock, so what will happen if the SOC throttles its clock, is APIC timer also affected by it

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Ravi
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Re: Intel Atom Elkhart Lake APIC Timer

Post by Octocontrabass »

Intel SDM wrote:If CPUID.06H:EAX.ARAT[bit 2] = 1, the processor’s APIC timer runs at a constant rate regardless of P-state transitions and it continues to run at the same rate in deep C-states.
CPUID says the APIC timer is not affected.
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Re: Intel Atom Elkhart Lake APIC Timer

Post by ravi »

Hello Octocontrabass



I tried to use TSC, by using CPUID 15, CPU base 2000, MAx 3000 and BASe = 100 this evaluated 150mhz i.e ~6.6 nanoseconds

but when i really start to use it micro second level , values are so off compared to PIT(which i have verified with a scope),, question is not in great detail i am still investigating this .. any suggestions

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Ravi
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Re: Intel Atom Elkhart Lake APIC Timer

Post by Octocontrabass »

ravi wrote: Mon Jun 24, 2024 3:35 pmI tried to use TSC, by using CPUID 15, CPU base 2000, MAx 3000 and BASe = 100
CPUID leaf 0x15 is correct, but those numbers don't look like they came from CPUID leaf 0x15.

To get the TSC frequency in Hz from CPUID leaf 0x15, calculate ECX * EBX / EAX. Your TSC frequency should be close to 2GHz.
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Re: Intel Atom Elkhart Lake APIC Timer

Post by ravi »

Prefect, thanks i think i confused myself with CUPID 16 data, now every thing make sense
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Re: Intel Atom Elkhart Lake APIC Timer

Post by ravi »

Hello Octocontrabass

question is quite odd

in my test code i have set up

1) PIT timer to 4msec and measured with scope, that interrupts every 4mesc
2) i take APIC timer count in every PIT timer intr, the count indicates 4msec
3) i take TSC timer count in every PIT timer intr, the count indicates 4msec

now
if i use these timers for small time measurements for example a "C" instruction with 4 assembly lines(MMIO read)

both show vastly different results
TSC says 52ns
APIC says 2.2us

my question is as far as you are aware of (both are invariant )

1) is APIC timer capable of measuring small measurements( it is ~26ns resolution )
2) what is you thought about TSC(it is`0.5ns resolution)

Thanks
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Re: Intel Atom Elkhart Lake APIC Timer

Post by Octocontrabass »

ravi wrote: Mon Jul 22, 2024 5:04 pm1) is APIC timer capable of measuring small measurements( it is ~26ns resolution )
I think so, but I've never tried it. If you use x2APIC, RDMSR and WRMSR are not serializing instructions, so you need additional serializing instructions for accurate measurements.
ravi wrote: Mon Jul 22, 2024 5:04 pm2) what is you thought about TSC(it is`0.5ns resolution)
RDTSC, RDTSCP, and RDMSR are not serializing instructions. You need additional serializing instructions for accurate measurements.
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Re: Intel Atom Elkhart Lake APIC Timer

Post by ravi »

Hello Octocontrabass

earlier, using CUPID along with APIC timer did not change anything, is there particular order in which i have to use lfence/sfence/mfence?

but now after you reminded me, i put CPUID along with TSC, it matched with APIC time thanks.

do you have any suggestions why MMIO operation are taking so much time for me

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Re: Intel Atom Elkhart Lake APIC Timer

Post by Octocontrabass »

ravi wrote: Mon Jul 22, 2024 10:57 pmearlier, using CUPID along with APIC timer did not change anything, is there particular order in which i have to use lfence/sfence/mfence?
If you use MMIO to access the APIC, it's already strongly-ordered relative to the MMIO you're trying to measure, so CPUID/LFENCE/SFENCE/MFENCE won't change anything. If you use MSRs to access the APIC, you can use something like "MFENCE; LFENCE; RDMSR; LFENCE;" to serialize. If you want to measure something that isn't strongly-ordered relative to MMIO, you might need to use "MFENCE; LFENCE; MOV; LFENCE;" for APIC MMIO.

Intel suggests this instruction sequence in the description of RDTSC in volume 2B of the SDM. (This is specific to Intel CPUs! You might need something different for AMD or others.)
ravi wrote: Mon Jul 22, 2024 10:57 pmdo you have any suggestions why MMIO operation are taking so much time for me
Each MMIO operation is a separate bus transaction, and bus transactions are slow. The only way to make it faster is to put more data in each bus transaction. DMA can put more data in each bus transaction, so you should use DMA if MMIO is too slow. (For things like display framebuffers, you can also use write-combining to put more data in each bus transaction.)
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Re: Intel Atom Elkhart Lake APIC Timer

Post by ravi »

thanks

DMA, as you know i tried for few days really i was stuck(but will continue to work on it again), eventually when the DMA works

1) our transactions are discreet, i mean is few bytes at time but continuously , some time 4 bytes some times 10 bytes, kind of command response stuff, my worry is i have to set DMA controller with different transaction lengths again and again doing MMIO with DMA controller,,, probably LLINk list method is the best so that i can set the main register values as oar of the list

thanks
Ravi
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