8259 PIC: Possible misinformation in listed source

[NotYourFox]

OSDev 8259 PIC (https://wiki.osdev.org/8259_PIC) article provides the following definitions in the code for reading ISR and IRR registers:

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#define PIC_READ_IRR                0x0a    /* OCW3 irq ready next CMD read */
#define PIC_READ_ISR                0x0b    /* OCW3 irq service next CMD read */

which, according to official manuals and other sources, is correct, however the listed source (https://helppc.netcore2k.net/hardware/8259) states the following:

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Operation Control Word 3   (Ports 20h & A0h)
   │7│6│5│4│3│2│1│0│  OCW3
	 │ │ │ │ │ │ │ └─── 1=read IRR on next read, 0=read ISR on next read
	 │ │ │ │ │ │ └──── 1=act on value of bit 0, 0=no action if bit 0 set
	 │ │ │ │ │ └───── 1=poll command issued, 0=no poll command issued
	 │ │ │ │ └────── must be 1 for OCW3
	 │ │ │ └─────── must be 0 for OCW3
	 │ │ └──────── 1=set special mask, 0=reset special mask
	 │ └───────── 1=act on value of bit 5, 0=no action if bit 5 set
	 └────────── not used (zero)

implying, that bit 0 of OCW3 should be clear, so the command word should be 0x0a.

Considering that the latter is the only source I've found saying that bit 0 should be clear, I believe it is a typo in that source.
I think, however, the mistake is worth being noted in the 8259 PIC article to prevent future readers from getting confused.

[nullplan]

In doubt, you should probably believe the Intel datasheet over the claims of random websites. In this case

The IRR can be read when, prior to the RD pulse, a Read Register Command is issued with OCW3 (RR = 1, RIS = 0.)
The ISR can be read, when, prior to the RD pulse, a Read Register Command is issued with OCW3 (RR = 1, RIS = 1).

So the values listed on the Wiki are correct and the netcore page is wrong.