I have a question about UEFI and PIC.
I have 6 testing computers, where 3 of them have UEFI.
I test UEFI with qemu too.
On QEMU and 2 of me real hardware,
Code: Select all
#define PIC1 0x20 /* IO base address for master PIC */
#define PIC2 0xA0 /* IO base address for slave PIC */
#define PIC1_COMMAND PIC1
#define PIC1_DATA (PIC1+1)
#define PIC2_COMMAND PIC2
#define PIC2_DATA (PIC2+1)
#define ICW1_ICW4 0x01 /* ICW4 (not) needed */
#define ICW1_SINGLE 0x02 /* Single (cascade) mode */
#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */
#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */
#define ICW1_INIT 0x10 /* Initialization - required! */
#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */
#define ICW4_AUTO 0x02 /* Auto (normal) EOI */
#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */
#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */
#define ICW4_SFNM 0x10 /* Special fully nested (not) */
uint8_t idtoffsetcode = 0x20;
uint8_t oldpic1 = inportb(PIC1_DATA);
uint8_t oldpic2 = inportb(PIC2_DATA);
outportb(PIC1, 0x11);
outportb(PIC2, 0x11);
outportb(PIC1_DATA, idtoffsetcode);
outportb(PIC2_DATA, idtoffsetcode + 8);
outportb(PIC1_DATA, ICW1_INTERVAL4);
outportb(PIC2_DATA, ICW1_SINGLE);
outportb(PIC1_DATA, ICW1_ICW4);
outportb(PIC2_DATA, ICW1_ICW4);
outportb(PIC1_DATA, 0x0);
outportb(PIC2_DATA, 0x0);
outportb(PIC1_DATA,oldpic1);
outportb(PIC2_DATA,oldpic2);
Does anyone have a idea how this is possible?