I'll reference an article from digitaltrends.com even though I think the way it bags on AMD is both inaccurate and shortsighted:
Quote:
a hybrid CPU combines performant (P) cores and efficient (E) cores onto a single processor. This design — known as big.LITTLE — was pioneered by chip designer ARM, and you can find it in nearly all mobile devices available today. Apple brought that design to laptops and desktops, and now Intel is following suit.
...
Intel sees the writing on the walls. The company hasn’t been shy about pointing out Apple as its true competitor in the future, not AMD. Meanwhile, AMD continues to stick with architectures that focus on fast cores and a lot of them instead of focusing on a hybrid approach.
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https://www.digitaltrends.com/computing ... lder-lake/You're correct that even for a performance core, lowering the clock and voltage gets you a disproportionate win for power draw. As the big CPU manufacturers get more competitive, they're looking even deeper for an edge, especially for mobile devices where performance is relegated to second priority under low power usage.
When a performance core is designed, it's given extra logic to run multiple instructions per clock. The IPC score achieved by a modern P-core when it has optimized code gets up to
about 5 for x86 and
about 7 for Apple arm. But here's the key - that extra physical hardware can't all be shut off when the core is running at low clocks and low voltage.
So the big CPU manufacturers have started adding little cores (E-cores) that are physically unable to chew through instructions at the same pace. But the E-cores have every trick in the book when it comes to efficiency:
- Smaller instruction decoder
- Fewer instruction-level parallelism "ports"
- Fewer entries in the reorder buffer
- Fewer cache prefetchers
- Smaller cache
- Transistor layouts are optimized for low power, at the expense of being slightly larger on-chip
- Transistor chemistry and geometry are optimized for low power, at the expense of not being able to run at the highest clock speeds
- Intel even left out the most expensive instructions (such as AVX-512) which caused some problems because a process could be running on a P-core, where it checked first and then decided to enable the AVX-512 code path. But then it got rescheduled by the OS on an E-core, where it immediately crashed.
If you're thinking a hybrid cpu with P-cores and E-cores is a big pain, you're not wrong! It seems we're going to be stuck with them though.
(Oh, and AMD has been really smart to adopt a wait-and-see approach here. AMD's chiplet innovations are paying off in spades while Intel wades through the morass of coming up with a decent hybrid design.)