Getting into long mode without paging

[Cyao]

Can I get into 64 bit mode without paging? Too lazy to learn and deal with it

[nexos]

No. You must either use paging or not use long mode.

You could achieve the same effect by identity mapping everything. But you'll still need to learn how to use paging.

[Octocontrabass]

You could use a bootloader that sets up paging for you, but then you're stuck with the bootloader's page tables until you learn how to set up your own.

[Cyao]

Okk thx, guess ill still have to deal with pagging

[AndrewAPrice]

I have not tried this but I wonder if you could identity map a PML4 to 512 GB pages. But it will be easy to identify map at the PML3 to 1GB pages. You'd only need 8KB of memory to map the bottom 512GB of virtual memory to physical memory.

[Octocontrabass]

I have not tried this but I wonder if you could identity map a PML4 to 512 GB pages. But it will be easy to identify map at the PML3 to 1GB pages. You'd only need 8KB of memory to map the bottom 512GB of virtual memory to physical memory.

You can map a PML4 to a 512GB page if you enable 5-level paging, but pages aren't allowed to span memory type boundaries, so you wouldn't be able to use it to identity-map memory on most PCs unless you also set the page to uncacheable.

You'll also run into this problem with 1GB and 2MB pages, but at least at those sizes it's easier to avoid.

[nexos]

I have not tried this but I wonder if you could identity map a PML4 to 512 GB pages.

Do you mean use the PS bit on PML4E's? I scanned the Intel manuals and it didn't say anything, so unless I'm missing something, I guess this isn't possible.

[Octocontrabass]

Huh, you're right, the Intel manuals don't say anything about it. My usual quick reference suggests it's possible; I wonder if Intel had originally planned to add it alongside 5-level paging and the page was never updated when Intel got rid of it...

[iansjack]

Can I get into 64 bit mode without paging? Too lazy to learn and deal with it

You may have chosen the wrong hobby.

[devc1]

This is a simple page table to start with, it identity maps 1gb of low memory using 2mb pages.

NASM Syntax,

align 0x1000
PageTable:
.Pml4:
dq .Pdp + 3 ; + 3 (or | 3 ) which set Present & R/W Bits
times 511 dq 0
.Pdp:
dq .Pd + 3
times 511 dq 0
.Pd: ; Identity Map low 1gb
%assign i 0
%rep 512
dq i + 0x83
%assign i i + 0x200000
%endrep

Remember, you will always need to make paging support.
So get up from your laziness and do it

[Cyao]

This is a simple page table to start with, it identity maps 1gb of low memory using 2mb pages.

NASM Syntax,

align 0x1000
PageTable:
.Pml4:
dq .Pdp + 3 ; + 3 (or | 3 ) which set Present & R/W Bits
times 511 dq 0
.Pdp:
dq .Pd + 3
times 511 dq 0
.Pd: ; Identity Map low 1gb
%assign i 0
%rep 512
dq i + 0x83
%assign i i + 0x200000
%endrep

Remember, you will always need to make paging support.
So get up from your laziness and do it

Ooo thx! I will eventually find some time to study it later, but ima go with this atm