Invalid TSS exception of which I can't see the origin

[aramya]

My problem is specifically with the context switching that must be done when an interrupt arrives in usermode: -d int indicates to me that a 0xa exception is happening.

Yet, I am certain that my TSS is well-formed, and that the ESP I'm providing is a correct address that is mapped as kernel's. Moreover, my interrupts handling is correctly called if I try to STI while still in kernel mode, which suggest that the problem comes exclusively from my TSS.

I really don't know from where this could come. Here is where I am setting up a TSS entry: https://github.com/thamugadi/mel/blob/main/gdt/gdt.c

Here is a dump of -d int -M smm=off : https://pastebin.com/PpA2irNP
I notice that it keeps jumping for no reason to 0xefb51 after the reset following the Invalid TSS exception.

Does anyone have any idea what's going on?

[Octocontrabass]

I don't know if this is the problem, but your TSS DPL should be 0.

I don't think this is the problem , but this inline assembly is wrong. It should look like this:

Code: Select all

asm( "ltr %w0" : : "r"(0x28) );

[MichaelPetch]

This looks suspicious unless I don't understand your memset. You set up the TSS by initializing members and then you set the whole thing to zero?

Code: Select all

        tss.ss0  = 0x10;
        tss.esp0 = 0x200000;
        tss.iopb = 104;

        memset(&tss, 0, 104); 

[aramya]

This looks suspicious unless I don't understand your memset. You set up the TSS by initializing members and then you set the whole thing to zero?

Code: Select all

        tss.ss0  = 0x10;
        tss.esp0 = 0x200000;
        tss.iopb = 104;

        memset(&tss, 0, 104); 

Sometimes I really don't pay attention to obvious things like that. Thank you very much for pointing this out: it solved the problem.