I was going through some documentation on MSI and came across some old chipset databooks that define a way for MSI-unaware operating systems to use MSI (as an alternative to legacy INTx emulation). Here is the relevant part from the Intel 5000X Memory Controller Hub datasheet:
I understand why the corresponding entry in the IOAPIC must be setup for edge triggered interrupts - the semantics of MSI closely match those of edge triggered interrupts. But wouldn't an MSI unaware operating system simply assume that that since it is a PCI INTx interrupt, it must be setup as level triggered, active low - thereby rendering this system useless? How is this supposed to work? What I'm worried about here is some old chipset having this mechanism while I, wanting to use legacy INTx interrupts, setup the IOAPIC pin for level triggered delivery, ultimately causing interrupts to not work.In this method, PCI Express devices are programmed to enable MSI functionality, and
given a write path directly to the pin assertion register in a selected IOxAPIC already
present in the platform. The IOxAPIC will generate an interrupt message in response,
thus providing equivalent functionality to a virtual (edge-triggered) wire between the
PCI Express endpoint and the I/OxAPIC. This mechanism is the same as is used in
Longhorn* (XYZZY).
All PCI Express devices are strictly required to support MSI. When MSI is enabled, PCI
Express devices generate a memory transaction with an address equal to the I/
OxAPIC_MEM_BAR + 20 and a 32-bit data equal to the interrupt vector number
corresponding to the device. This information is stored in the device's MSI address and
data registers, and would be initialized by the system firmware (BIOS) prior to booting
a non-MSI aware operating system. (With the theory that an MSI aware O/S would
then over-write the registers to provide interrupt message delivery directly from the
endpoint to the CPU complex.)
The interrupts associated with the PCI Message-based interrupt method must be set up for edge
triggered mode, rather than level triggered, since the peripheral only does the write to indicate the
edge.
