How to write a TSS (in assembly)

[kzinti]

I can sort of perhaps see that it aligns with the 32-bit TSS, and its offsets for ESP[0,1,2], but why did they have to? They literally had no compatibility baggage to worry about.

What do you base that conclusion on? It seems to me that this would simplify the hardware design. It totally makes sense to keep both structures aligned to re-use common silicon paths. Not that I know how it was implemented... Perhaps they just wanted to re-use part of the existing design and copy it somewhere else on the chip. Who knows what other hardware constraints / optimizations are relevant here?

For example, it is very likely that the "io map" of both structures are driven by the same silicon or the same design. Hence it makes sense for them to be in the same location and format. It also probably make it possible to reuse the same validation tests.

[Schol-R-LEA]

Also, it's written in C and generated at runtime. I'm not a fan of that.

[...] you could create 255 TSS segments statically [...] It isn't more complicated than to create 256 IDT entries statically.

Yes, but isn't that a moot point, though? It is easy enough to have a dynamically generated TSS in assembly using (assuming NASM, which is what rizxt is using) the struc directive to define the structure.

Code: Select all

struc Task_State_Segment
    .reserved_0              resd 1        
    .RSP                     resq 3          ; RSP0 - RSP2
    .reserved_1              resq 2
    .interrupt_stack_table   resq 7          ; IST1 - IST7
    .reserved_2              resq 2
    .reserved_3              resw 1
    .IOPB_offset             resw 1
endstruc 

You can define the structure with that, then set aside memory space for it at runtime from some preset pool.

If you definitely want some or all of them to be defined statically, you can still use an istruc to initialize it at assemble time.

Code: Select all

TSS_0:
    istruc Task_State_Segment
        at reserved_0,             dd 0        
        at RSP,                    dq ring0, ring1, ring2 
        at reserved_1,             dd 0
        at interrupt_stack_table,  dq i1, i2, i3, i4, i5, i6, i7             
        at reserved_2,             dd 0
        at reserved_3,             dw 0    
        at IOPB_offset,            dw quux
    iend 

You might want to define one or more macros for manipulating the RSP and IST arrays.

[austanss]

I must mention this thread has grown irrelevant for me as I have managed to write a functional TSS, although not in assembly. Currently I am working on syscalls, namely configuring the stack on entry.

Your insight is still welcome.

[Schol-R-LEA]

Ah, just as well; I realized I'd made at least one mistake in my post (which I corrected, but there may be others).

[sj95126]

You can easily generate the TSS from Assembly

It's not even that hard. I dynamically generate a TSS and add it to the GDT in about 15 or so assembly instructions.