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Hi, I have a few questions about PCI once again:
1. Can I access PCIe configuration space with 8/16/64 bit reads/writes?
2. Can I access PCIe devices bars with 8/16/64 bit reads/writes?
3. When I try to read the amount of address space required for a BAR for an AHCI controller, I get back 0x1000 after all conversions.
However, I know that an AHCI HBA memory space takes up to 0x1100 if all ports are present. Am I reading the value wrong or is that
intended? (I get 0x1000 on both VMWare and QEMU)
8infy wrote:Hi, I have a few questions about PCI once again:
1. Can I access PCIe configuration space with 8/16/64 bit reads/writes?
2. Can I access PCIe devices bars with 8/16/64 bit reads/writes?
3. When I try to read the amount of address space required for a BAR for an AHCI controller, I get back 0x1000 after all conversions.
However, I know that an AHCI HBA memory space takes up to 0x1100 if all ports are present. Am I reading the value wrong or is that
intended? (I get 0x1000 on both VMWare and QEMU)
1. No, you can only access PCI(e) config space with 8/16/32 bit read/writes, not 64bit ones.
2. Yes, although this is per device and per register, in general you should never access MMIO with unaligned accesses.
3. Probably intended, AHCI is not required to implement all 32 ports, which I don't think QEMU or VMWare do, so they have no use for such a large MMIO space.
8infy wrote:1. Can I access PCIe configuration space with 8/16/64 bit reads/writes?
The PCI and PCIe configuration space allows 8/16/32-bit reads and writes that do not cross 32-bit boundaries.
8infy wrote:2. Can I access PCIe devices bars with 8/16/64 bit reads/writes?
You can access BARs with 8/16/32-bit reads and writes that do not cross 32-bit boundaries. (But BARs are 32-bit registers, so why wouldn't you use 32-bit accesses?)
8infy wrote:3. When I try to read the amount of address space required for a BAR for an AHCI controller, I get back 0x1000 after all conversions. [...] Am I reading the value wrong or is that intended?
It's intended. AHCI controllers are allowed to request different amounts of space depending on how many registers are implemented.
