uhci is not processed horizontal queue

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Klakap
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uhci is not processed horizontal queue

Post by Klakap »

I am back on programming operation system and I am still working on UHCI. Now I am confused what happens in QEMU. I trying to read device configuration descriptor. SETUP packet is send right. IN packets are transferred right. But when SPD occurs, execution is not moved on horizontal in queue to OUT package but transfer next IN packet with 0 transferred bytes and execution ends. Here is Bochs dump(I think it is more useful than my code):

Code: Select all

00053883980d[UHCI ] Global Reset
00053883980d[UHCI ] Schedule bit clear in Command register
00053919422d[UHCI ] register write to  address 0xC020:  0x00000000 (16 bits)
00053919422d[UHCI ] Schedule bit clear in Command register
00053956294d[UHCI ] register write to  address 0xC020:  0x00000002 (16 bits)
00053956294d[UHCI ] Schedule bit clear in Command register
00054097097d[UHCI ] register write to  address 0xC020:  0x00000000 (16 bits)
00054097097d[UHCI ] Schedule bit clear in Command register

00054133970d[UHCI ] register write to  address 0xC024:  0x00000000 (16 bits)
00054133991d[UHCI ] register write to  address 0xC026:  0x00000000 (16 bits)
00054134014d[UHCI ] register write to  address 0xC028:  0x01400000 (32 bits)
00054134035d[UHCI ] register write to  address 0xC02C:  0x00000040 ( 8 bits)
00054134056d[UHCI ] register write to  address 0xC022:  0x0000FFFF (16 bits)
00054134056d[UHCI ] write to status register with bits 15:6 not zero: 0xffff

00054134077d[UHCI ] register write to  address 0xC030:  0x00000200 (16 bits)
00054134077d[UHCI ] write to port #1 register bit 7 = 0
00054134077i[UHCI ] Port1: Reset
00054335109d[UHCI ] register write to  address 0xC030:  0x00000000 (16 bits)
00054335109d[UHCI ] write to port #1 register bit 7 = 0
00054371992d[UHCI ] register write to  address 0xC030:  0x0000000F (16 bits)
00054371992d[UHCI ] write to one or more read-only bits in port #1 register: 0x000f
00054371992d[UHCI ] write to port #1 register bit 7 = 0
00054408865d[UHCI ] register write to  address 0xC032:  0x00000200 (16 bits)
00054408865d[UHCI ] write to port #2 register bit 7 = 0
00054408865i[UHCI ] Port2: Reset
00054610007d[UHCI ] register write to  address 0xC032:  0x00000000 (16 bits)
00054610007d[UHCI ] write to port #2 register bit 7 = 0
00054646890d[UHCI ] register write to  address 0xC032:  0x0000000F (16 bits)
00054646890d[UHCI ] write to one or more read-only bits in port #2 register: 0x000f
00054646890d[UHCI ] write to port #2 register bit 7 = 0
00054683760d[UHCI ] register read from address 0xC030:  0x000005A5 (16 bits)
00054683787d[UHCI ] register read from address 0xC030:  0x000005A5 (16 bits)
# set address
00054708802d[UHCI ] register write to  address 0xC026:  0x00000000 (16 bits)
00054708822d[UHCI ] register write to  address 0xC020:  0x00000081 (16 bits)
00054708822d[UHCI ] Schedule bit set in Command register
00054712000d[UHCI ] Queue   0: 0x00000000 0 1  0x01402020 0 0
00054712000d[UHCI ] Frame: 0000 (0x0000)
00054712000d[UHCI ] QH001:TD found at address: 0x01402020
00054712000d[UHCI ]   01402044   04800000   00E0002D   01404010
00054712000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054712000d[UHCI ] Frame: 0000 (0x0000)
00054712000d[UHCI ] QH001:TD found at address: 0x01402040
00054712000d[UHCI ]   00000001   04800000   FFE80069   01404000
00054712000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0000
00054874848d[UHCI ] register read from address 0xC020:  0x00000081 (16 bits)
00054874873d[UHCI ] register write to  address 0xC020:  0x00000080 (16 bits)
00054874873d[UHCI ] Schedule bit clear in Command register
# read configuration
00054958092d[UHCI ] register write to  address 0xC026:  0x00000000 (16 bits)
00054958112d[UHCI ] register write to  address 0xC020:  0x00000081 (16 bits)
00054958112d[UHCI ] Schedule bit set in Command register
00054960000d[UHCI ] Queue   0: 0x01402280 0 0  0x01402020 0 0
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402020
00054960000d[UHCI ]   01402044   04800000   00E0012D   01404000
00054960000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402040
00054960000d[UHCI ]   01402064   04800000   00E80169   01404010
00054960000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402060
00054960000d[UHCI ]   01402084   04800000   00E00169   01404018
00054960000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402080
00054960000d[UHCI ]   014020A4   04800000   00E80169   01404020
00054960000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014020A0
00054960000d[UHCI ]   014020C4   04800000   00E00169   01404028
00054960000d[UHCI ]  r_actlen = 0x0008 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014020C0
00054960000d[UHCI ]   014020E4   04800000   00E80169   01404030
00054960000d[UHCI ]  r_actlen = 0x0002 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014020E0
00054960000d[UHCI ]   01402104   04800000   00E00169   01404038
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402100
00054960000d[UHCI ]   01402124   04800000   00E80169   01404040
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402120
00054960000d[UHCI ]   01402144   04800000   00E00169   01404048
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402140
00054960000d[UHCI ]   01402164   04800000   00E80169   01404050
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402160
00054960000d[UHCI ]   01402184   04800000   00E00169   01404058
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402180
00054960000d[UHCI ]   014021A4   04800000   00E80169   01404060
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014021A0
00054960000d[UHCI ]   014021C4   04800000   00E00169   01404068
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014021C0
00054960000d[UHCI ]   014021E4   04800000   00E80169   01404070
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014021E0
00054960000d[UHCI ]   01402204   04800000   00E00169   01404078
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402200
00054960000d[UHCI ]   01402284   04800000   00E80169   01404080
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0008
00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x01402280
00054960000d[UHCI ]   00000001   04800000   FFE801E1   01404000
00054960000d[UHCI ]  r_actlen = 0x0000 r_maxlen = 0x0000
00055122928d[UHCI ] register read from address 0xC020:  0x00000081 (16 bits)
00055122953d[UHCI ] register write to  address 0xC020:  0x00000080 (16 bits)
00055122953d[UHCI ] Schedule bit clear in Command register
Thank for any help!
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BenLunt
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Re: uhci is not processed horizontal queue

Post by BenLunt »

Klakap wrote:

Code: Select all

00054960000d[UHCI ] Frame: 0000 (0x0000)
00054960000d[UHCI ] QH001:TD found at address: 0x014020C0
00054960000d[UHCI ]   014020E4   04800000   00E80169   01404030
00054960000d[UHCI ]  r_actlen = 0x0002 r_maxlen = 0x0008
You are not setting bit 29 in the Status DWORD (DWORD1). To enable Short Packet Detect, bit 29 must be set.

Ben
- http://www.fysnet.net/the_universal_serial_bus.htm
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Klakap
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Joined: Sat Mar 10, 2018 10:16 am

Re: uhci is not processed horizontal queue

Post by Klakap »

Thank you! Somehow I did not know this. Now my driver works well in QEMU so I decided to try it on my test computer. I do it and something strange happen. Reset and enabling port works well, SETUP and OUT packages are send well, but IN packages have set active bit and have set CRC timeout bit. Please why is it?
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