MP Tables and PCI bus

[8infy]

Hi, I stumbled upon this weirdness in PCI assignment entries in MP tables (I get similar results on all software i've tested on like QEMU/VMWare)

As you can see I have 2 PCI devices from the same bus ID, both INTAs, but different IOAPIC destination pins! How is that possible?

InterruptController: I/O Interrupt Assignment entry:
----> Type: Vectored Interrupt
----> Polarity: Active High
----> Trigger mode: Conforming
----> Source bus ID: 0 (PCI)
----> Source bus IRQ: 4 (INTA, Device number 1)
----> Destination IOAPIC id: 0
----> Destination IOAPIC pin: 9 <--------------------------------- PIN 9 here

InterruptController: I/O Interrupt Assignment entry:
----> Type: Vectored Interrupt
----> Polarity: Active High
----> Trigger mode: Conforming
----> Source bus ID: 0 (PCI)
----> Source bus IRQ: 12 (INTA, Device number 3)
----> Destination IOAPIC id: 0
----> Destination IOAPIC pin: 11 <--------------------------------- PIN 11 here

The 4 and 12 for source bus IRQ you see are not actually IRQ numbers, but are bit fields, with the format described on this picture (from the mp spec):

Could you please explain what I'm doing wrong or if maybe this is actually possible....

[Octocontrabass]

As you can see I have 2 PCI devices from the same bus ID, both INTAs, but different IOAPIC destination pins! How is that possible?

Didn't we already go over this? PCI is different from ISA.

[8infy]

As you can see I have 2 PCI devices from the same bus ID, both INTAs, but different IOAPIC destination pins! How is that possible?

Didn't we already go over this? PCI is different from ISA.

Right. But now that I'm reading about PCI specifically I was under the impression that INTA/B/C/D are 4 letters that correspond to 4 unique IOAPIC pins, is that not how that works?

[Octocontrabass]

No, the four letters correspond to four pins in the PCI slot. Each slot can have those four pins wired to a different set of four IOAPIC pins.

[8infy]

No, the four letters correspond to four pins in the PCI slot. Each slot can have those four pins wired to a different set of four IOAPIC pins.

Thanks, this makes sense. So each device has 4 of these, and they're connected to different ioapic pins. What got me confused in the first place is this part of the PCI article https://wiki.osdev.org/PCI#IRQ_Handling, it makes it seem like all 4 of those are unique and you get all IRQs on the same IOAPIC pin for each letter. If that's not the case then what's the problem that this article is describing? You know exactly which device caused the IRQ this way...

[8infy]

No, the four letters correspond to four pins in the PCI slot. Each slot can have those four pins wired to a different set of four IOAPIC pins.

Okay I think I got it after reading the article you sent. So PCI bus indeed produces 4 unique IRQs but for different devices on the bus INTA can mean different IRQ numbers depending on the position. Is that correct?

[Octocontrabass]

I think the author of that section was trying to describe that PCI IRQs can be mapped differently between PIC and IOAPIC, so you can't use the IRQ routing information from the configuration space since it only applies to PIC and not IOAPIC.

The author of that section added the following note when they added it to the wiki:

I don't know wheter the informations are correct and it'd be better if someone reads/corrects/improves this.

So PCI bus indeed produces 4 unique IRQs but for different devices on the bus INTA can mean different IRQ numbers depending on the position. Is that correct?

That's correct. It's also possible for devices to share IOAPIC pins, or each get their own IOAPIC pins that aren't shared at all.

[8infy]

I think the author of that section was trying to describe that PCI IRQs can be mapped differently between PIC and IOAPIC, so you can't use the IRQ routing information from the configuration space since it only applies to PIC and not IOAPIC.

The author of that section added the following note when they added it to the wiki:

I don't know wheter the informations are correct and it'd be better if someone reads/corrects/improves this.

So PCI bus indeed produces 4 unique IRQs but for different devices on the bus INTA can mean different IRQ numbers depending on the position. Is that correct?

That's correct. It's also possible for devices to share IOAPIC pins, or each get their own IOAPIC pins that aren't shared at all.

Awesome, thanks!