caching behavior for address spaces mapped to video memory

[ITchimp]

In James molloy's tutorial, as well as many other tutorials... 0xb8000, the starting address for
vga memory... that particular address was mapped into virtual address with cache fully turned on
and set to write back mode.. but 0xb8000 is actually memory on the vga card ... isn't caching supposed
to be disabled.... or it just doesn't matter and inconsequential?

I heard that doing dma often requires disabling caching...

Can someone explain the caching behavior in the context of IO?

[nullplan]

For framebuffers, the appropriate cache mode is write-combining. Note that the cache mode is governed not only by the page table bits, but also - if enabled - by the page attribute table, and by the MTRRs. I would suspect that firmware is setting up the MTRRs to declare the cache mode of the VGA region to be write-combining. In that case, the memory type will combine with whatever you set up in paging to be either write-combining or uncacheable. In no case do you get write-back caching.

I heard that doing dma often requires disabling caching...

Not on x86. On x86, a DMA actor takes part in the exact same cache coherency protocol the CPUs do, which means caches are invalidated before being read and after being written. From a programmer's point of view, DMA just works.

Can someone explain the caching behavior in the context of IO?

I presume firmware sets the MTRRs for MMIO regions to uncacheable. Then paging cannot turn caching back on, no matter what you set up.

[Octocontrabass]

In James molloy's tutorial, as well as many other tutorials... 0xb8000, the starting address for
vga memory... that particular address was mapped into virtual address with cache fully turned on
and set to write back mode.. but 0xb8000 is actually memory on the vga card ... isn't caching supposed
to be disabled.... or it just doesn't matter and inconsequential?

On modern PCs, the firmware has already configured the MTRRs to override WB in the page tables and disable caching where necessary. The firmware's provided configuration will work, but it may not be optimal - for example, you usually want frame buffers configured as WC, but firmware might set them up as UC.

VGA memory accesses can have side effects, so the firmware will configure it as UC. If you're using it as a dumb frame buffer, you can reconfigure the MTRRs or the page tables to use WC.

You must follow the appropriate procedures to update cache settings in the page tables and in the MTRRs or you risk causing a machine check exception. Some combinations of cache settings between MTRRs and the page tables or between two overlapping MTRRs are undefined behavior, so read the manual carefully.

I heard that doing dma often requires disabling caching...

On x86, usually not. Most x86 hardware automatically maintains cache coherency. If x86 hardware does require you to change cache settings, it will be documented clearly.

Can someone explain the caching behavior in the context of IO?

Most I/O should not be cached. Frame buffers are the only exception I'm aware of, and even then you only want WC and not WB caching. Lucky for you, very old PCs didn't have caches at all, so modern PCs automatically set everything up so you can mostly ignore the caches if you want. (But your frame buffer might be faster if you use WC...)