I/O APIC vector redirection issue

[iman]

Hi.

I have disabled PIC and enabled LAPIC and I/O APIC for my OS on physical machine.
Previously, with PIC, I had IRQ0 for PIT and IRQ1 for keyboard. Now during the I/O APIC initialization, first I assumed all ISA IRQs are remapped with the same numbering to I/O APIC, but only keyboard interrupts work and there is no PIT timer signal. Then to make sure that IRQ0 is mapped to I/O APIC INTIN0 or not, I parsed the MP config table and found all the information for I/O Interrupt Assignment Entries, as partly shown in the enclosed image.

Here is the issue:
There are two entries labeled as IRQ0 (shown with arrow). One has interrupt type ExtINT and mapped to INTIN0 and the second one goes to INTIN2 with type INT.
It does not matter if I remap the vectors during my I/O APIC initialization as:

Code: Select all

remap_vect(0, (0 + 32), EDGE, HIGH);

or

Code: Select all

remap_vect(0, (2 + 32), EDGE, HIGH);

There in no timer interrupt.

notes:
1-my system shows no ACPI table labeled as MADT
2-I would not be interested to work with LAPIC timer
image:

Best.
Iman.

[bellezzasolo]

The MADT isn't labelled 'MADT'. It's labelled 'APIC'.
That should help...

[iman]

The MADT isn't labelled 'MADT'. It's labelled 'APIC'.
That should help...

it was a typo. I meant APIC signature.
Basically my machine supports only ACPI with signatures "FACS" and "DSDT".

[thomtl]

Basically my machine supports only ACPI with signatures "FACS" and "DSDT".

That is weird since those are both of the tables that aren't accessed through the RSDT or XSDT but found through the FADT.

[iman]

The MADT isn't labelled 'MADT'. It's labelled 'APIC'.
That should help...

I had a look at your apic initialization code from your github.
I did a similar approach to bring the apic into usage instead of pic. My dedicated goal now is to get PIT and keyboard interrupts from I/O APIC.
The steps look something like this in my code:

Code: Select all

1- cli and disable_pic
2- get lapic base address from MSR
3- write to the SVR register
4- mask all local interrupts (timer, thermal sensor, ...)
5- enable ioapic by:
    1- mask all interrupts (from 0 up to 23 which I could get from max_entries)
    2- remap those irqs that you want, to the destination ioapic pins provided in io interrupt assignment entries got from MP table (I have irq0 to be remapped into INTIN2 and irq1 to INTIN1) and unmask them by clearing bit 16
    3- even though all irq handlers had been set before, once more install irq0 and irq1 handlers
    4- sti

keyboard interrupts are fine, but I still cannot get any PIT interrupt.
note: sending EOI have been handled, as well.