correct output by qemu | incorrect output by bochs
00000000: 0c0f 0104 0e03 1a11 1912 001c 0009 0e06 │ 00000000: 6c6f 6164 2e63 3a31 3932 207c 2049 6e66
00000010: 0f00 1c00 0f13 0c0f 0104 0512 1f0d 0109 │ 00000010: 6f20 7c20 6f73 6c6f 6164 6572 5f6d 6169
00000020: 0e0c 0005 0e14 0512 0a0c 0f01 040e 031a │ 00000020: 6e2c 2065 6e74 6572 0a6c 6f61 642e 633a
it seems that bits[7:5] are set to 0
my serial port initialization code :
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#define UART_COM1 (0x3F8)
#define UART_COM2 (0x2F8)
#define UART_DATA (0x0) // data register.
#define UART_DIVL (0x0) // with DLAB set to 1, least significant byte of
// divisior for baud rate.
#define UART_DIVM (0x1) // with DLAB set to 1, most significant byte.
#define UART_INTE (0x1) // interrupt Enable register
#define UART_INTI (0x2) // interrupt identification
#define UART_FCRL (0x2) // FIFO control registers
#define UART_LCRL (0x3) // Line Control Register
// most significant bit of this register is DLAB
#define UART_MCRL (0x4) // Modern Control Register
void uart_init()
{
x86_outb(UART_COM1 + UART_INTE, 0x00); // disable all intrrupt
x86_outb(UART_COM1 + UART_LCRL, 0x80); // Set DLAB
x86_outb(UART_COM1 + UART_DIVL, 0x03); // set least significant byte of divisor to 0x03
x86_outb(UART_COM1 + UART_DIVM, 0x00); // set most significant byte of divisor to 0
x86_outb(UART_COM1 + UART_LCRL, 0x03); // 8 bits, no parity, one stop bit
x86_outb(UART_COM1 + UART_FCRL, 0xc7); // FIFO
x86_outb(UART_COM1 + UART_MCRL, 0x0b); // IRQs enabled, RTS/DSR set
}
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ata0-master: type=disk, path=build/img.bin
boot: disk
com1: enabled=1, mode=file, dev=com1.log
log: bochs.log
gdbstub: enabled=1
Does any one have suggesions? thanks in advance