Moving the IDT/GDT/TSS

[AndrewAPrice]

If I move the IDT, GDT, or TSS in physical memory but it stays mapped to the same location in linear memory, do I need to call lidt/lgdt/ltr so the CPU picks it up?

[bzt]

No, the CPU uses so called shadow registers. These are just like cache. When you use lgdt for example, it reads the memory and fills up those shadow registers. After that one could zero out the GDT in RAM, the CPU will still work correctly.
This goes for GDT/LDT/IDT, not entirely sure about TSS though. I believe shadow registers are not used when ISP is enabled, but I could be wrong on this part.

Cheers,
bzt

[Octocontrabass]

If I move the IDT, GDT, or TSS in physical memory but it stays mapped to the same location in linear memory, do I need to call lidt/lgdt/ltr so the CPU picks it up?

No. Since the linear address isn't changing, there's no need to reload any registers.

No, the CPU uses so called shadow registers. These are just like cache. When you use lgdt for example, it reads the memory and fills up those shadow registers. After that one could zero out the GDT in RAM, the CPU will still work correctly.
This goes for GDT/LDT/IDT, not entirely sure about TSS though.

This is wrong. The CPU does not cache the GDT, LDT, IDT, or TSS. The CPU does cache segment descriptors, which are used by the ordinary segment registers (CS/DS/ES/FS/GS/SS) as well as the LDTR and TR. Loading a selector into any of the aforementioned registers requires a valid descriptor table to be present so the CPU can fill that register's shadow register, even if the selector refers to a descriptor already in one of the shadow registers.

[bzt]

The CPU does not cache the GDT, LDT, IDT, or TSS. The CPU does cache segment descriptors

Then what are those GDTR, LDTR, IDTR, LTR things that the AMD spec calls "Descriptor-Table Registers" in Volume 2 section 6.3, and Intel refers to as "Memory Management Registers" in Volume 3a section 2.4? Just asking, because those are definitely NOT cache segment descriptors.

But frankly, I don't see any benefit why would one move GDT/IDT/TSS, and even if you do move them, be paranoid, assume you must refresh everything and no surprises on real (sometimes buggy) hardware.

Cheers,
bzt

[Octocontrabass]

Then what are those GDTR, LDTR, IDTR, LTR things that the AMD spec calls "Descriptor-Table Registers" in Volume 2 section 6.3, and Intel refers to as "Memory Management Registers" in Volume 3a section 2.4? Just asking, because those are definitely NOT cache segment descriptors.

They are segment registers.

CS, DS, ES, FS, GS, SS, LDTR, and TR all work the same way. You can read or write a selector value into them, and when you write a selector value, the hidden portion (or "descriptor cache") is loaded from the descriptor table with that segment's base, limit, and other attributes.

GDTR and IDTR work differently. These two registers do not have segment selectors. Instead, when you read and write them, you are directly accessing the segment base and limit values that are hidden in the other segment registers. (They have no other attributes, since those are unnecessary for GDT and IDT segments.)

[AndrewAPrice]

But frankly, I don't see any benefit why would one move GDT/IDT/TSS

I was thinking about DMA, and how to handle it in my microkernel in a very generic way that doesn't know about the specifics of DMA. So I'm thinking if having a syscall such as "allocate X of memory below linear address Y", and if the kernel can't find unallocated memory, it can move things out of the way. So, I'm covering my bases to see what could potentially break if I moved the kernel's virtual memory out of the way.

[bzt]

@Octocontrabass: please read the referenced parts of the specs.

@AndrewAPrice: I see. In this case my advice is to reload all system registers (segments too) and no surprise will come to you. Even if reloading some of them wouldn't be a must it won't hurt either. As I understand this would only happen once when the first DMA buffer is needed and the memory is already used for something else, so you shouldn't worry about performance at all.

As a general role, I would advice every time you read in a spec that "system software SHOULD", read it as "system software MUST". This will save you from lots of trouble on different hardware.

Cheers,
bzt

[Octocontrabass]

@Octocontrabass: please read the referenced parts of the specs.

I have, but I don't see where I've said anything that disagrees with them.