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#define FWCFG_DMA_READ 2
fwcfg_dma_access(file.select << 16 | FWCFG_DMA_READ, ramfb_file.size, (vaddr_t) &cfg);
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#if __ORDER_LITTLE_ENDIAN__
#define HTOBE(x) __builtin_bswap32(x)
#define HTOBE64(x) __builtin_bswap64(x)
#else
#define HTOBE(x) x
#define HTOBE64(x) x
#endif
#define FW_CFG_BASE 0x09020000
#define FW_CFG_CTL_OFF 0x08
#define FW_CFG_DATA_OFF 0x00
#define FW_CFG_DMA_OFF 0x10
struct fwcfg_dma_access {
uint32_t control;
uint32_t length;
uint64_t address;
};
static vaddr_t _addr(vaddr_t base, vaddr_t offset)
{
return (vaddr_t) phys_to_virt(base, MEM_AREA_IO_SEC) + offset;
}
int fwcfg_dma_access(uint32_t ctrl, uint32_t len, vaddr_t addr)
{
volatile struct fwcfg_dma_access access;
access.control = HTOBE(ctrl);
access.length = HTOBE(len);
access.address = HTOBE64(addr);
vaddr_t access_addr = (vaddr_t) virt_to_phys((void*) &access);
uint32_t access_addr_lo = (uint32_t) (access_addr & 0xFFFFFFFFU);
uint32_t access_addr_hi = (uint32_t) (access_addr >> 32);
io_write32(_addr(FW_CFG_BASE, FW_CFG_DMA_OFF), HTOBE(access_addr_hi));
io_write32(_addr(FW_CFG_BASE, FW_CFG_DMA_OFF + 4), HTOBE(access_addr_lo));
DMSG("Waiting on DMA Access");
while ((HTOBE(access.control) & ~FWCFG_DMA_ERROR) != 0) {}
DMSG("DMA Access Done");
return FWCFG_OK;
}
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DMSG("Waiting on DMA Access");
while (io_read32(_addr(FW_CFG_BASE, FW_CFG_DMA_OFF)) != 0) {}
DMSG("DMA Access Done");