[SOLVED] ATA DMA driver problem

[vhaudiquet]

Hello everyone !
I have a working ATA PIO driver, but it is really slow, and since i have a scheduler i started to make an ATA DMA driver.
I followed the specs in "idems100.pdf" file and http://wiki.osdev.org/ATA/ATAPI_using_DMA on the wiki, but i'm stuck.
I end up waiting for an interrupt that never comes.
I'm using QEMU to test my kernel ; i did not test it on real hardware (because i can't right now) but i don't think that the problem comes from qemu.

The code is a bit messy, and some things that i should do during initialisation are done in the read function, but i really want to perform one working read and after that i'll clean up the whole thing.
If you want to read it, it's all on github : https://github.com/Valou3433/vk/blob/ma ... /ata_dma.c
I do :
- prepare a PRDT, with a pointer to a physical adress that is not aligned (is that a problem ? i'll fix that later but i don't know ; anyway i tried with aligned address it doesnt change anything)
- read BAR4 to get the ports
- reset start/stop bit
- send physical PRDT address
- set read bit in bus master command register
- clear err/interrupt bit
- select the drive (and send top 4 bits of LBA28 address)
- clean drive error port
- send sector count (which is actually one on the read that i have tried)
- send the rest of the LBA28 address
- poll for the drive BSY bit (is that really usefull ?)
- send DMA transfer command
- set the start/stop bit
- wait for an IRQ, that never comes (i know i should add a timeout in that case, but anyway the dma read doesnt work)

Am i doing something wrong ? i tried to find code samples or documentation, but they are really obscure about the whole thing...
Thanks for reading and trying to help me !

[BenLunt]

Sorry, I don't have the time to look over your code at the moment, but real quick, did you set the Enable Bus Master I/O bit in the PCI Command register?

Ben

[vhaudiquet]

i tried to enable or disable every possible bit in the pci command register ; but every attempt did nothing except change the value of that pci register (the irq did not come)
i wonder : what bit is that (0-7) ?
and as i tried to enable every possible bit, during multiple attempts, i don't think that this is the source of my problem.
i think that i misunderstood something or that there is a problem in my code, my implementation...

[vhaudiquet]

Alright, little update : i tried my code on virtual box and i'm getting an interrupt ; the problem is maybe in qemu or in something that i don't set and that is active by default on virtualbox.
I'll try to debug the whole thing, but if you have any idea why it would do that, i'm taking it...
Anyway thanks for help !

[vhaudiquet]

Okay, in the end, problem solved ! I'm really bad, the problem was in my PIC irq handling code : i was sending EOI (end of interrupt) only to the master pic and not the slave !
Because of that, after the first ATA interrupt, the slave pic never sent other interrupts...

[BenLunt]

We all have had moments like this. Thinking it was one thing and it was something completely different. I had an "off by 1" issue I just couldn't figure out one time.

Anyway, just as a note, make sure to EOI the slave before you EOI the master.

Ben