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Or should I wait a transfer to complete, then start a new one? In other words can I do more than two transfers same time / one is not completed yet? Or should I only do one transfer at a time, and wait transfer to finish with a semaphore, mutex, etc.
If I can do more than two transfers same time, should I do anything special? Is running it as usual enough?
Thanks in advance
Last edited by Agola on Mon Mar 13, 2017 1:09 pm, edited 1 time in total.
Agola wrote:Now, for ATA, can I do a new DMA read while other is working? I couldn't find anything about it in Busmaster DMA documentation. (Documentation is: http://www.osdever.net/downloads/docs/idems100.zip)
That depends. Typically there are 2 ATA controllers (primary and secondary) that are considered "independent" (even though it's likely they're both part of the same chip), where each controller can have 2 drives (master and slave), and each controller has its own bus mastering.
There are 4 cases:
You can't do multiple DMA transfers at the same time from the same drive (but may be able to queue up multiple transfers to run one after the other, if both transfers are "read" or if both are "write").
You can't do multiple DMA transfers at the same time from different drives that are attached to the same ATA controller. This is a restriction caused by "2 devices share the same cable".
You should (if the hardware isn't buggy) be able to do multiple DMA transfers at the same time from drives that are attached to different ATA controllers; because the ATA controllers are independent.
If I remember correctly (unfortunately I can't find where I read this); there are some buggy ATA controllers where you can't do multiple DMA transfers at the same time using different ATA controllers without problems.
Agola wrote:Or should I wait a transfer to complete, then start a new one? In other words can I do more than two transfers same time / one is not completed yet? Or should I only do one transfer at a time, and wait transfer to finish with a semaphore, mutex, etc.
While one command is in progress you shouldn't touch any of the bus master's registers. This means that you can't/shouldn't add a second transfer after setting the "start/stop bus master" flag and before the IRQ occurs.
Cheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.
Agola wrote:Now, for ATA, can I do a new DMA read while other is working? I couldn't find anything about it in Busmaster DMA documentation. (Documentation is: http://www.osdever.net/downloads/docs/idems100.zip)
That depends. Typically there are 2 ATA controllers (primary and secondary) that are considered "independent" (even though it's likely they're both part of the same chip), where each controller can have 2 drives (master and slave), and each controller has its own bus mastering.
There are 4 cases:
You can't do multiple DMA transfers at the same time from the same drive (but may be able to queue up multiple transfers to run one after the other, if both transfers are "read" or if both are "write").
You can't do multiple DMA transfers at the same time from different drives that are attached to the same ATA controller. This is a restriction caused by "2 devices share the same cable".
You should (if the hardware isn't buggy) be able to do multiple DMA transfers at the same time from drives that are attached to different ATA controllers; because the ATA controllers are independent.
If I remember correctly (unfortunately I can't find where I read this); there are some buggy ATA controllers where you can't do multiple DMA transfers at the same time using different ATA controllers without problems.
Agola wrote:Or should I wait a transfer to complete, then start a new one? In other words can I do more than two transfers same time / one is not completed yet? Or should I only do one transfer at a time, and wait transfer to finish with a semaphore, mutex, etc.
While one command is in progress you shouldn't touch any of the bus master's registers. This means that you can't/shouldn't add a second transfer after setting the "start/stop bus master" flag and before the IRQ occurs.
