io base and mem base?

[szhou42]

Hi, I am following this tutorial trying to implement networking for my os.
http://wiki.osdev.org/Intel_Ethernet_i217

I am not sure how it reads the io_base and mem_base because the constant PCI_BAR_IO and PCI_BAR_MEM is not known.
Is it just extracting the base address from bar0?

I am also very confused that there are 6 BARs, how one knows which is the right one to get info about base address and bar_type?

Code: Select all

E1000::E1000(PCIConfigHeader * p_pciConfigHeader) : NetworkDriver(p_pciConfigHeader)
{
    // Get BAR0 type, io_base address and MMIO base address
    bar_type = pciConfigHeader->getPCIBarType(0);
    io_base = pciConfigHeader->getPCIBar(PCI_BAR_IO) & ~1;
    mem_base = pciConfigHeader->getPCIBar( PCI_BAR_MEM) & ~3;    
 
    // Off course you will need here to map the memory address into you page tables and use corresponding virtual addresses
 
    // Enable bus mastering
    pciConfigHeader->enablePCIBusMastering();
    eerprom_exists = false;
}

Thanks in advance

[Kevin]

I am also very confused that there are 6 BARs, how one knows which is the right one to get info about base address and bar_type?

It just depends on the hardware. If you read the spec of a PCI device, it will tell you which BAR is used for what. If the wiki article is right, this specific PCI device uses BAR0 to map its registers.

I am not sure how it reads the io_base and mem_base because the constant PCI_BAR_IO and PCI_BAR_MEM is not known.
Is it just extracting the base address from bar0

The call looks weird to me, but essentially you need to read the BAR from the config space, check the flags to find out whether it's I/O ports or MMIO, and mask out the flags and reserved bits to get the base address. Normally the spec tells you whether it uses I/O ports or MMIO, but apparently for this device, different models use different BAR types, so you'd have to detect it.

[SpyderTL]

In your case, PCI_BAR_IO and PCI_BAR_MEM should both be hexadecimal values 0x10. Probably.

The source code to PCIConfigHeader isn't included on this wiki article...