dumb/noob question regarding IO/APIC redirection

[stdcall]

Am I a total dump noob or when a I read a redirection entry such as IRQ 0 --> IRQ 2 in ACPI tables,
It means that IRQ0 will be redirected to IRQ2 in IOAPIC.
But what happens now to IRQ2 ? where does it go ? to the same input ?

It doesn't make sense that there's no corresponding IRQ2 redirection then.

[BrightLight]

Am I a total dump noob or when a I read a redirection entry such as IRQ 0 --> IRQ 2 in ACPI tables,
It means that IRQ0 will be redirected to IRQ2 in IOAPIC.
But what happens now to IRQ2 ? where does it go ? to the same input ?

It doesn't make sense that there's no corresponding IRQ2 redirection then.

Nothing happens to IRQ 2, because in the legacy PIC configuration, IRQ 2 is the cascade interrupt. The master PIC is connected to the CPU, and the slave PIC is connected to IRQ 2 on the master. On the IOAPIC, there are no need for a cascade IRQ, thus IRQ 0 (timer) is remapped to IRQ 2, and the local APIC timer is mapped to IRQ 0.

[jnc100]

local APIC timer is mapped to IRQ 0.

Do you have a reference for this? As far as I was aware, IOAPIC interrupt 0 is signalled whenever the southbridge/ICH raises an interrupt, and is thus used for any interrupts where the ICH doesn't raise a separate interrupt line. The only example of this I can find is when using external FPU interrupts (which are routed from the builtin FPU in the CPU to the ICH and then back to the IOAPIC).

Regards,
John.

[BrightLight]

local APIC timer is mapped to IRQ 0.

Do you have a reference for this? As far as I was aware, IOAPIC interrupt 0 is signalled whenever the southbridge/ICH raises an interrupt, and is thus used for any interrupts where the ICH doesn't raise a separate interrupt line. The only example of this I can find is when using external FPU interrupts (which are routed from the builtin FPU in the CPU to the ICH and then back to the IOAPIC).

I don't recall where I read this, but I have indeed handled a local APIC timer IRQ 0 using I/O APIC on QEMU before.

[mariuszp]

Wrong.

Each CPU (or CPU core) as its own local APIC, and they do not generate IRQs; they signal interrupts on the CPU that they are on.

And you can actually choose which specific interrupt vector the APIC timer triggers, by programming the value into a bitfield in the LVT entry for the timer - it is the same register that decides which mode (single-shot, periodic, etc) the APIC timer is in. This is documented in section 10.5.4 of the Intel System Programming Manual. For the format of an LVT entry, see section 10.5.1 - it tells you which entry is for the timer, and as you can see in the table, the bottom 8 bits select the interrupt vector it should trigger. You have to do this separately for each CPU.