Depending on the device, the specs say that it could take up to 30 seconds for the drive to be ready.
The ATAPI 6.0 specs say that you must have bit 2 set for no less than 5uS, then wait no less than 2uS after clearing it.
Then the device should move to the "HSR2: Check_status State". This is where the busy bit will be set until the drive is ready and then will move to the "HI0: Host_Idle State".
If you are reading a zero from the status register, then I don't know what to tell you other than check your delay code to make sure you are waiting that long.
The specs also say to read the Error Register to see if there was a successful reset (ending status).
Ben
ATAPI interrupt problem
Re: ATAPI interrupt problem
Hi Ben,
Maybe I'm waiting too long. I checked the Error Register before and after the reset. Before the reset its value was 0 and after it was 1. As I know it can be the Illegal Length Indicator bit or Command Time Out bit. I'll try to make a more accurate sleep function using cpu timers.
Br,
Andrej
Maybe I'm waiting too long. I checked the Error Register before and after the reset. Before the reset its value was 0 and after it was 1. As I know it can be the Illegal Length Indicator bit or Command Time Out bit. I'll try to make a more accurate sleep function using cpu timers.
Br,
Andrej
Re: ATAPI interrupt problem
If you read the ATAPI6 specs, while in the DIAG state, after a reset, and before a drive ready, it states:
If you are reading zero from the status register, then you are reading it at this state, the drive is not busy, and it may or may not yet be ready for commands.
Then shortly later, the specs state:
You should now be ready to send a command. What does the other registers contain? The device should have set these registers to their respective signature values while in the DIAG state mentioned above.
Remember, you must select a drive before you can read the registers from it. There is only one set of I/O registers, but a possibility of two devices each containing matching registers. You must tell the controller which device you wish to read/write to.
Ben
Meaning that all but the BUSY bit and bit 1 (obsolete) will be zero.If the device implements the PACKET command feature set, the device shall clear bits 6, 5, 4, 3, 2, and 0 in the Status register to zero.
If you are reading zero from the status register, then you are reading it at this state, the drive is not busy, and it may or may not yet be ready for commands.
Then shortly later, the specs state:
Next, you need to select a drive. A drive will not become ready until you select it. After reset, both devices (including the second one if present) will just be coming out of the reset state and neither will be selected.When hardware initialization and self-diagnostic testing is completed and the status has been set, the device shall clear BSY to zero and make a transition to the DI1: Device_idle_S state
You should now be ready to send a command. What does the other registers contain? The device should have set these registers to their respective signature values while in the DIAG state mentioned above.
Remember, you must select a drive before you can read the registers from it. There is only one set of I/O registers, but a possibility of two devices each containing matching registers. You must tell the controller which device you wish to read/write to.
Ben