Is there any CPU with big endian of BIT order ?

[miaowei]

do you know any cpu that designed as big endian of bit order.
take care, what i said is 'BIT' order

[miaowei]

sorry, may be i have misconcepts about bit order.
when the data is transmited through a cable (e.g. network), what's the minium unit of the transmision. BYTE or BIT ?

[SpyderTL]

Bit order would only matter with a serial connection, like a USB device or a Network adapter. Everything else is transmitted in parallel, meaning that each bit is sent over a separate physical wire, and another signal wire is used to notify the recipient when all of the data bit wires should be read.

So, internally, it doesn't matter what order the bits are processed inside the CPU -- it only matters when data is transferred to some other component, like system RAM. Of course, the RAM doesn't really care about what bits are set, or what those bits mean, either, when it comes to the data being stored. It only cares about the address data bits, and it's really up to the CPU and motherboard hardware to make sure that the address data bits are connected and delivered properly.

Now, if you were to actually swap the order of bits inside the CPU, logically, then a few bitwise operations would no longer make sense, like Left Shift and Right Shift. But that would be a simple matter of just swapping the names of those instructions, so that Left Shift actually shifts bits to the right, and vice versa. But I'm not aware of any CPUs where a Left Shift actually shifts bits toward the Least Significant Bit. I think that would be like having an ADD instruction that subtracted one operand from another.

[Rusky]

Bit orderings are meaningless to CPUs because you don't address individual bits, and when you do it's in terms of most/least significant rather than any kind of external addressing that could have its order swapped. (The one exception I know of is bit set/test instructions that need to map indices to bits in some particular order, but that's not a very fundamental part of the CPU design.)

Where bit ordering is relevant is low-level data transmission protocols. For example, Ethernet and USB send the least-significant bit first, while I2C sends the most significant bit first (see here).

[miaowei]

Bit order would only matter with a serial connection, like a USB device or a Network adapter.

yes, it is when i was writing a tcp/ip stack that made me think of this question.

and it's really up to the CPU and motherboard hardware to make sure that the address data bits are connected and delivered properly.

can i explain my question from another angle?
suppose there two byte(a word) in the RAM like:

Code: Select all

<==============<===============  address growth
                             0x7c01               0x7c00
_________________________________
0  0  0  0  0  0  0  0  1  0  0  0  0  0  0  1 0
----------------------------------------------------------

from the view of x86 cpu, the word's value(i.e *(unsigned short*)0x7c00 ) is 0x0102.
from the view of MIPS cpu, the word's value is 0x0201.
But, is there another kind of cpu in the world that treats this word as 0x8040, or 0x4080 ?

[BrightLight]

from the view of x86 cpu, the word's value(i.e *(unsigned short*)0x7c00 ) is 0x0102.
from the view of MIPS cpu, the word's value is 0x0201.
But, is there another kind of cpu in the world that treats this word as 0x8040, or 0x4080 ?

I don't think so. Endianness applies to multi-byte fields, like WORDs, DWORDs and QWORDs. I don't think you have big endian and little endian bits.

[mariuszp]

Bit order would only matter with a serial connection, like a USB device or a Network adapter.

yes, it is when i was writing a tcp/ip stack that made me think of this question.

and it's really up to the CPU and motherboard hardware to make sure that the address data bits are connected and delivered properly.

can i explain my question from another angle?
suppose there two byte(a word) in the RAM like:

Code: Select all

<==============<===============  address growth
                             0x7c01               0x7c00
_________________________________
0  0  0  0  0  0  0  0  1  0  0  0  0  0  0  1 0
----------------------------------------------------------

from the view of x86 cpu, the word's value(i.e *(unsigned short*)0x7c00 ) is 0x0102.
from the view of MIPS cpu, the word's value is 0x0201.
But, is there another kind of cpu in the world that treats this word as 0x8040, or 0x4080 ?

That wouldn't make sense.

If you write the byte 0x40 to memory, how could you logically expect the value to be read back as 0x08?

"From the view of MIPS cpu..." NO.

That word is 0x7C00, from the view of ANY CPU. If we have the word at address 0x10, the address at that word is 0x7C00, from the perspective of whatever CPU wrote it. The only difference is if we address it in smaller cunks: addresses 0x10 and 0x11 will contain the byte 0x7C and 0x00, but not necessarily in that order. However, addressing that field as a word at 0x10 always yields 0x7C00. "Bit order" would only matter if we could address individual bits, just like byte order only amtters because we can address individual bytes.

As for sending that over the network... the NIC will divide the message into bytes, and handle ordering of bits sent on the wire; the CPU will not care because, again, it can't access individual bits on the packet received by the NIC; but it CAN address individual bytes, so network byte order is important.

[SpyderTL]

If the bits were "flipped" to make bit 0 the Most Significant Bit in the CPU, then it would simply be the job of the motherboard manufacturer to make sure that the "wires" that connected the CPU to the memory controller were "flipped" as well, so that they ended up wired up to the correct pins. Also, as I said before, the memory chip doesn't care what the bits mean to the CPU. It simply stores them, as is.

It would only matter to other devices that were reading directly from system memory, like PCI devices. In that case, it would be up to the software to "flip the bits" before storing them in system memory so that the hardware would read the data properly, which is essentially what you have to do now, when writing your network driver.

But as far as I know, there are no CPUs that work this way. Interestingly, there are some 4-bit CPUs out there, though.

[Octocontrabass]

There are CPUs with bit numbering both ways, but it doesn't actually change anything. No matter what number you assign to each bit, the MSB is the MSB and the LSB is the LSB.