Normally; yes you can assume that only higher priority IRQs can interrupt lower priority interrupt handlers. However note that IRQ priorities go in an "awkward" order for historical reasons - e.g. from highest priority to lowest, it's "IRQ0, 1, 8, 9, 10, 11, 12, 13, 14, 15, 3, 4, 5, 6, IRQ7".onlyonemac wrote:Should I assume that the higher-order interrupts thus take priority over the lower-order ones? In other words, if I get a second interrupt before I've returned from the first, may I assume that it is a higher-order interrupt? Another way to word this is: if I get an interrupt and I haven't yet sent an EOI, may I assume that only higher-order interrupts will be passed to the CPU and that lower-order ones will be discarded/queued until the first interrupt is handled? (Sorry for asking this so many different ways but I'm wanting to make sure that I'm clear on this because accessible documentation on the topic seems scant.)
Abnormally; the PIC has various modes that are almost never used on PCs ("auto-EOI", "rotating priority mode", etc) that break this. In addition it's possible for a kernel's IRQ handler to mask the IRQ and send EOI initially, then handle the interrupt, then unmask the IRQ. This breaks the PIC's priority scheme, and I doubt there's ever a sane reason to do this (but I'm sure there's at least one kernel I've seen in the past that does this - possibly an old version of MINIX).
Finally; the PIC's spurious IRQs are a little strange, and it's best to just assume they ignore the PIC's IRQ priority scheme.
Cheers,
Brendan