I know many people will ignore this post when they see the title, because they know it. But I still post here, because i hope to help some one like me.
I have wasted over a week on a bug due to this.(Don't laugh at me)
At first, i thought bochs is not that clever to emulate TLB, but it does.
And I didn't pay much attention to TLB(I believe it's transparent), this is another cause .
and I also want to share my happiness with you now ^.^
(Beijing night 8:38)
share a bug: remember flush your TLB when writing page table
Re: share a bug: remember flush your TLB when writing page t
Yup...
And after flushing the TLB, depending on the architecture, you may also need to invalidate the data-cache, instruction cache, and branch predictor.
Maybe even flush the pipeline!
And after flushing the TLB, depending on the architecture, you may also need to invalidate the data-cache, instruction cache, and branch predictor.
Maybe even flush the pipeline!
Re: share a bug: remember flush your TLB when writing page t
Hi,
One week to find a bug like this isn't unusual at all.
Cheers,
Brendan
TLB invalidation bugs are nearly always "Heisenbugs" - random/confusing symptoms that are different on different hardware and disappear or change when you try to investigate; where it's painfully difficult to figure out the actual cause.miaowei wrote: I have wasted over a week on a bug due to this.(Don't laugh at me)
One week to find a bug like this isn't unusual at all.
Cheers,
Brendan
For all things; perfection is, and will always remain, impossible to achieve in practice. However; by striving for perfection we create things that are as perfect as practically possible. Let the pursuit of perfection be our guide.