No explicit ss register in the gdt ?

[JulienDarc]

Hello,

My question is 64-bit related.

I see everywhere that there is no SS register descriptor in the gdt, just CS and DS register descriptors.

The Intel manual, volume 1, chapter 3, page 14 (top), says :

Unlike the CS register, the SS register can be loaded explicitly, which permits application programs to set
up multiple stacks and switch among them.

Ok, so as a general rule, the cpu is smart enough to set the registers dynamically, except CS and DS.
And there is no need for an explicit descriptor for those.

I just want to validate the knowledge, because otherwise i cannot learn

Thanks for this great learning place ,

Julien

[Brendan]

Hi,

My question is 64-bit related.

I see everywhere that there is no SS register descriptor in the gdt, just CS and DS register descriptors.

What you see is a GDT entry that describes a "generic read/write not executable" area, which is probably used for SS, DS and ES. It's not specifically for DS alone. Note: For 64-bit code in long mode, the CPU ignores the segment base and limit but does not ignore attributes and permissions and therefore you still need GDT entries for SS, DS, ES, etc.

The Intel manual, volume 1, chapter 3, page 14 (top), says :

Unlike the CS register, the SS register can be loaded explicitly, which permits application programs to set
up multiple stacks and switch among them.

Basically all Intel are saying here is that there is no "mov cs,ax" instruction (like "mov ss,ax" and "mov ds,ax"). This instruction doesn't exist because it rarely makes sense to change CS without changing IP, and in the (extremely rare) cases where it's useful a "jmp far" is good enough.


Cheers,

Brendan

[JulienDarc]

Thanks Brendan,

You made it crystal clear

[ExeTwezz]

Note: For 64-bit code in long mode, the CPU ignores the segment base and limit but does not ignore attributes and permissions and therefore you still need GDT entries for SS, DS, ES, etc.

Actually, the GS and FS registers are exceptions, so the CPU doesn't ignore their base addresses in the GDT, as says 3.4.2.1 of Volume 1.

Edit: s/in the GDT//

[madanra]

Actually, the GS and FS registers are exceptions, so the CPU doesn't ignore their base addresses in the GDT, as says 3.4.2.1 of Volume 1.

I thought FS and GS used a base address stored in an MSR, rather than the GDT? (See SWAPGS, WRFSBASE, WRGSBASE etc.)