Memory Management - the layout of page tables in memory.

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HyperAssembler
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Memory Management - the layout of page tables in memory.

Post by HyperAssembler »

Hi all,
Today I wrote my own map_page function. I used the compact model. See figure below.

0x0 -[PML4]
--------------------
0x1000 -[PDPT]
--------------------
0xF000 -[PD]
--------------------
--------------------
0x1F000 -[PT]
(Memory addrs are hypothetical)

It basically means page tables are put in continuous pages and adjacent to each other(uses at little memory as possible). The actual size for each table is based on the total memory I have. E.g. I have 513G mem, then 2x PML4 entries, 513 * PDPT entries, and so forth.
So that when I call map_page, if a page does not exist, the map_page function itself can handle can create new entries needed.

My question is whether this layout is robust/ would there be any problems if I use this model everywhere?
(My designed thought was that there was no point dispersing tables throughout the VIRTUAL ADDRESS SPACE and more importantly, I don't want map function to take 6-7 parameters just to specify everything).

Thanks for your time.!
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Re: Memory Management - the layout of page tables in memory.

Post by alexfru »

If you don't want to waste RAM, you should only map page frames and allocate required page tables only when necessary, and not all in advance.

If you want to have more than one address space and/or virtual memory, you can't base the number of page tables or PTEs simply on the amount of physical memory. You should allow for more virtual memory than physical (use disk storage for swapping) and for sharing memory (by mapping the same page frame in address spaces of different processes).

If you want to be able to change page tables and directories in a convenient manner (as opposed to having special mappings just for PTE manipulations), you should consider making a cycle in the page table hierarchy (AKA recursive page tables). Of course, this will only work at the levels, where PTEs have the same format (IOW, below PML4).

OTOH, at this early point you probably don't need 64-bit mode or even page translation. Ultimately it all depends on what you want, what you can do and where you are now.
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Re: Memory Management - the layout of page tables in memory.

Post by Combuster »

This scheme is broken in the sense that it only supports one address space with exactly contiguous memory. You end up being unable to map pages to everything that isn't RAM (like video memory), and you can't logically separate the heap and stack in memory.

page tables are put in continuous pages and adjacent to each other(uses at little memory as possible).
That is nonsense. Whichever memory you use for a page table doesn't change that you used exactly one page table of memory. If you want to save memory on page tables, use larger page sizes.
and more importantly, I don't want map function to take 6-7 parameters just to specify everything).
You'll only need three parameters: map virtual address X to physical address Y, with flags Z. You can write a function around that which takes just one parameter: a virtual address that needs to be allocated.
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HyperAssembler
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Re: Memory Management - the layout of page tables in memory.

Post by HyperAssembler »

page tables are put in continuous pages and adjacent to each other(uses at little memory as possible).
That is nonsense. Whichever memory you use for a page table doesn't change that you used exactly one page table of memory. If you want to save memory on page tables, use larger page sizes.

Ahh, "use as little mem as possible" means that if you only have 32G of RAM, I only need to allocate 1 PML4, 32(1024) PDPT and so on, so that I don't need to worry about the second 1024 PDPT entries that the second PML4 corresponds to.
and more importantly, I don't want map function to take 6-7 parameters just to specify everything).
You'll only need three parameters: map virtual address X to physical address Y, with flags Z. You can write a function around that which takes just one parameter: a virtual address that needs to be allocated.[/quote]

The problem is what if PML4 or PDPT or PD does not exist? Isn't map or alloc_v_addr(as you suggested) supposed to create new entries? If alloc_v_addr only takes one param, how does it know where to write new missing entries?

Or could I just create identity mapping for each process first, then map pages using that as base, then the problem above wouldn't happen.
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