PCI Address Spaces
PCI Address Spaces
I have a question about the PCI. The PCI has three address spaces; PCI I/O, PCI Memory and PCI Configuration space. Where are they each physically located? In the PCI controller? Or in the devices? Is any of them part of the system RAM?
- thepowersgang
- Member
- Posts: 734
- Joined: Tue Dec 25, 2007 6:03 am
- Libera.chat IRC: thePowersGang
- Location: Perth, Western Australia
- Contact:
Re: PCI Address Spaces
None are RAM, they're all (essentially) distinct busses.
IO space is on the x86 IO bus, MMIO is on the same bus as RAM (but at different addresses to RAM chips), and the configuration space is accessed via the PCI configuration bus (which on x86 is accessed using an Index-Data IO register pair, 0xCF8 and 0xCFC - other architectures may memory-map this bus)
IO space is on the x86 IO bus, MMIO is on the same bus as RAM (but at different addresses to RAM chips), and the configuration space is accessed via the PCI configuration bus (which on x86 is accessed using an Index-Data IO register pair, 0xCF8 and 0xCFC - other architectures may memory-map this bus)
Kernel Development, It's the brain surgery of programming.
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Re: PCI Address Spaces
So are they address spaces or buses? I'm a little confused. If I store something in PCI Memory for example, where will it be stored? According to what you're saying it sounds like it will be stored in the devices (the bus is attached to the devices and the bus itself doesn't have memory... Or does it?).thepowersgang wrote:None are RAM, they're all (essentially) distinct busses.
Also, when I read from a port using the "in" instruction, does that have anything to do with the PCI bus?
Re: PCI Address Spaces
The PCI bus can intercept any memory or I/O read or write from the CPU, if needed. It will always intercept read/write access to I/O ports 0xCFC and 0xCF8. It will intercept other ports and addresses if it has been configured by the BIOS or the OS to do so.
And, yes, the PCI bus has its own memory, just like most devices in your machine.
And, yes, the PCI bus has its own memory, just like most devices in your machine.
Project: OZone
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott
Re: PCI Address Spaces
There is alot I don't know about the PCI bus and the wiki doesn't explain it. Where can I learn about the PCI from the ground up?
Re: PCI Address Spaces
The wiki entry is actually pretty good. I think I used it primarily for my PCI code.
The official specs are at the bottom of that page, along with a lot of other links you can try.
Maybe if you ask a specific question, we can help you out a little more.
All you really need to do is loop through every number between 0 and 0xffff and get the Vendor ID for that port number. If the Vendor ID is not 0xFFFF, then there is a device on that port. You can then get additional device information for each connected port. Not too difficult.
The official specs are at the bottom of that page, along with a lot of other links you can try.
Maybe if you ask a specific question, we can help you out a little more.
All you really need to do is loop through every number between 0 and 0xffff and get the Vendor ID for that port number. If the Vendor ID is not 0xFFFF, then there is a device on that port. You can then get additional device information for each connected port. Not too difficult.
Project: OZone
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott
Re: PCI Address Spaces
The wiki is good for people who know something about the PCI already. But I don't even know where the values that I write to these address spaces are stored. I don't know that much about buses altogether (besides for the TLP stuff).
- thepowersgang
- Member
- Posts: 734
- Joined: Tue Dec 25, 2007 6:03 am
- Libera.chat IRC: thePowersGang
- Location: Perth, Western Australia
- Contact:
Re: PCI Address Spaces
Sorry, yes, they are separate address spaces.
PCI "memory" is just whatever device is listening on that address. Some device registers will keep their value, others are read-only, others are write-clear (write a mask of bits to clear), others are overloaded (with reads returning one register, and writes modifying another).
Basically, PCI is a set of specs (the electrical bus specification, the configuration interface, bridges to other busses, etc).
PCI "memory" is just whatever device is listening on that address. Some device registers will keep their value, others are read-only, others are write-clear (write a mask of bits to clear), others are overloaded (with reads returning one register, and writes modifying another).
Basically, PCI is a set of specs (the electrical bus specification, the configuration interface, bridges to other busses, etc).
Kernel Development, It's the brain surgery of programming.
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Re: PCI Address Spaces
The values are stored at I/O ports 0xCFC and 0xCF8. Always.Isaac wrote:The wiki is good for people who know something about the PCI already. But I don't even know where the values that I write to these address spaces are stored. I don't know that much about buses altogether (besides for the TLP stuff).
Just write the "address" you want to 0xCF8 and read the value from 0xCFC.
The high bit has to be set in order to get data back, so to get the Device and Vendor ID for the first PCI slot, just pass 0x80000000 to I/O port 0xCF8 and then read a 32-bit value from 0xCFC.
Give it a shot and let us know if you run into any problems.
Project: OZone
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott
Source: GitHub
Current Task: LIB/OBJ file support
"The more they overthink the plumbing, the easier it is to stop up the drain." - Montgomery Scott