GDTR linear address to physical address

[Dinesh]

In x86 architecture, lgdt instruction loads linear address of GDT and limit of gdt. Now for the conversion of linear to physical address does every task's page table contain the entry of GDT's linear address ? Is GDT's linear address shared by every task in the system ? If then every page directory should have the entry for GDT's linear address. Isn't ?

[iansjack]

Why would a task need to know the address of the GDT, let alone try to access it?

[Dinesh]

Say a task has executed a JMP instruction (JMP ptr16:32), then the task has to refer GDT for descriptor of 16 bit selector specified in instruction. In which case GDT's linear address is to be mapped into physical address by page directory of task. So my question is does all the tasks in the system share GDT's linear address and map them to same physical address using their own page directories ?

[iocoder]

If your tasks are allowed to modify segment registers on their own, then yes GDT should be mapped at the linear address to which GDTR register refers. In this case you may simply let GDT appear in the address space of every process, although some may argue that this is a bad design.

[Dinesh]

Do you mean to say only tasks which can modify segment registers on their own have access to GDT's linear address and have this listed in their page directory ?

But to switch task "The DPL of the TSS descriptor or task gate must be numerically greater (e.g., lower privilege level) than or equal to the maximum of CPL and the RPL of the gate selector. Exceptions, interrupts, and IRET are permitted to switch tasks regardless of the DPL of the target task gate or TSS descriptor. "(80386 programmer's reference manual http://pdos.csail.mit.edu/6.893/2009/re ... s07_05.htm)

Which means that they should access GDT to atleast check the privilege level right ?

And moreover the GDT's fundamental existence is to be accessible to all task in the system. Isn't ?


Note: I am a newbie trying to build my OS after a theory course at university.

[Dinesh]

And moreover segment loading instructions are not privileged instructions.

[iansjack]

Say a task has executed a JMP instruction (JMP ptr16:32), then the task has to refer GDT for descriptor of 16 bit selector specified in instruction. In which case GDT's linear address is to be mapped into physical address by page directory of task. So my question is does all the tasks in the system share GDT's linear address and map them to same physical address using their own page directories ?

But the task doesn't need to know the address of the GDT. It refers to segments by an index, not an address. it just asks the processor to load (say) the third entry in the GDT. The processor can access the GDT using its physical address but that is transparent to the task.

[iocoder]

Do you mean to say only tasks which can modify segment registers on their own have access to GDT's linear address and have this listed in their page directory ?

But to switch task "The DPL of the TSS descriptor or task gate must be numerically greater (e.g., lower privilege level) than or equal to the maximum of CPL and the RPL of the gate selector. Exceptions, interrupts, and IRET are permitted to switch tasks regardless of the DPL of the target task gate or TSS descriptor. "(80386 programmer's reference manual http://pdos.csail.mit.edu/6.893/2009/re ... s07_05.htm)

Which means that they should access GDT to atleast check the privilege level right ?

And moreover the GDT's fundamental existence is to be accessible to all task in the system. Isn't ?


Note: I am a newbie trying to build my OS after a theory course at university.

I think that was why they invented LDT

Say a task has executed a JMP instruction (JMP ptr16:32), then the task has to refer GDT for descriptor of 16 bit selector specified in instruction. In which case GDT's linear address is to be mapped into physical address by page directory of task. So my question is does all the tasks in the system share GDT's linear address and map them to same physical address using their own page directories ?

But the task doesn't need to know the address of the GDT. It refers to segments by an index, not an address. it just asks the processor to load (say) the third entry in the GDT. The processor can access the GDT using its physical address but that is transparent to the task.

But the processor accesses GDT using a linear address not a physical one and paging applies here. Doesn't it?

[Dinesh]

iansjack
As you said, yes they refer segments by index not address. GDTR contains linear address. To this linear address the 8*index is added to get the descriptor. The processor does not know it's physical address unless MMU translates this using page directory. My question is " Is GDT's linear address is mapped into every task's page directory for translation to happen ? "

[Dinesh]

iocoder
Ya LDT is local for that task as the name implies. My question is as global descriptor table is used by all tasks then linear address in GDTR should be mapped in all tasks page directory. In which case they all should point to same page directory. Isn't ?

[iansjack]

You told the processor the physical address of the GDT when you used the LGDT instruction to initialize it; that stored the physical address in the GDTR register. A logical address is not necessary when accessing the GDT as the physical address is already stored in that register; the processor uses that when you access the GDT.

[iocoder]

My question is " Is GDT's linear address is mapped into every task's page directory for translation to happen ? "

In my own kernel design, yes; GDT is mapped into every task's address space at the same linear address. Whenever a segment register is loaded with a new value, my x86 CPU accesses the GDT using current page directory pointed to by cr3. However, I don't think (or I don't know if) it is a must, as I said above

[iocoder]

You told the processor the physical address of the GDT when you used the LGDT instruction to initialize it; that stored the physical address in the GDTR register. A logical address is not necessary when accessing the GDT as the physical address is already stored in that register; the processor uses that when you access the GDT.

Weird The i386 programmer's reference manual (page 330) says linear o.O Or I miss something?

The LGDT and LIDT instructions load a linear base address and limit
value from a six-byte data operand in memory into the GDTR or IDTR,
respectively.

[iansjack]

Fair enough. I'll leave you to it.

[Brendan]

Hi,

I didn't read everything above, so...

Anyway; because of IRQs (and NMI), the CPU must be able to access a valid GDT and IDT at (almost) all times. This is typically done by putting the GDT in kernel space and mapping the kernel space into every virtual address space, so that the GDT is the same regardless of which virtual address space is currently being used.

The LGDT and SGDT instructions use a linear address. This is not necessarily the same as a virtual address (if you use segmentation), and not necessarily the same as a physical address (if you use paging).

To convert a linear address into a physical address; if paging is not being used then it's simple ("physical = linear"); and if paging is being used then you'd need to follow the page tables, etc (just like the CPU would). In both cases (with or without paging) it makes no difference what you do with segments.

Fortunately, there's typically no reason to care which physical addresses the GDT happens to be using. More likely is that you want to determine which virtual address the GDT is using. In this case, if you don't use segmentation then it's simple (virtual = linear), and if you do use segmentation then the gates of hell will open up and take your soul, so it's not really worth worrying about the GDT in that case.


Cheers,

Brendan