Problem setting VGA mode.

[Roman]

I tried to rewrite write_regs from this to assembly with hardcoded regs from g_320x200x256, but it doesn't work.

Code: Select all

	mov al, 0x63
	out 0x3C2, al
	
	mov al, 0x00
	out 0x3C4, al
	mov al, 0x03
	out 0x3C5, al
	
	mov al, 0x01
	out 0x3C4, al
	out 0x3C5, al
	
	mov al, 0x02
	out 0x3C4, al
	mov al, 0x0F
	out 0x3C5, al
	
	mov al, 0x03
	out 0x3C4, al
	mov al, 0x00
	out 0x3C5, al
	
	mov al, 0x04
	out 0x3C4, al
	mov al, 0x0E
	out 0x3C5, al
	
	mov al, 0x03
	out 0x3D4, al
	in al, 0x3D5
	or al, 0x80
	out 0x3D5, al
	mov al, 0x11
	out 0x3D4, al
	in al, 0x3D5
	and al, (~0x80)
	out 0x3D5, al
	
	mov al, 0
	mov rbx, crtc_regs
.crtc_reg_w_l:
	out 0x3C4, al
	push rax
	mov al, [rbx]
	out 0x3C5, al
	pop rax
	
	inc rbx
	inc al
	cmp al, 25
	jb .crtc_reg_w_l
	
	mov r15b, al
	
	mov al, 0
	mov rbx, gc_regs
.gc_reg_w_l:
	out 0x3CE, al
	push rax
	mov al, [rbx]
	out 0x3CF, al
	pop rax
	
	inc rbx
	inc al
	cmp al, 9
	jb .gc_reg_w_l
	
	mov al, 0
	mov rbx, ac_regs
.ac_reg_w_l:
	push rax
	in al, 0x3DA
	pop rax
	out 0x3C0, al
	push rax
	mov al, [rbx]
	out 0x3C0, al
	pop rax
	
	inc rbx
	inc al
	cmp al, 21
	jb .ac_reg_w_l
	
	in al, 0x3DA
	mov al, 0x20
	out 0x3C0, al
	
	cli
	hlt
...
...
...
crtc_regs db 0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0xBF, 0x1F, 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0x0E, 0x8F, 0x28,    0x40, 0x96, 0xB9, 0xA3, 0xFF

gc_regs db 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, 0xFF

ac_regs db 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x41, 0x00, 0x0F, 0x00, 0x00

When this code is executed, the cpu is in long mode.

What's wrong with this code, and why doesn't it set the video mode to 320x200x256?

[xenos]

If you run your code in Bochs, it should give you some helpful log output.

[Gigasoft]

You are writing values that should go in the CRTC registers, into the sequencer registers instead. By the way, there is no need to bother with CRTC reg 3 bit 7. This bit does nothing. Some very old code might mess with it due to being designed to handle EGA as well.

[Roman]

You are writing values that should go in the CRTC registers, into the sequencer registers instead. By the way, there is no need to bother with CRTC reg 3 bit 7. This bit does nothing. Some very old code might mess with it due to being designed to handle EGA as well.

I fixed this, but it still doesn't work