Edge semantics mean a billion different things but this question is mostly based on pc/at x86 architecture using an ioapic. Not the isa 8259 or eisa pic.
This isn't something I plan to implement or do, it is a question based purely on curiosity.
Since the ioapic recognizes edges at a well defined point in time (bottom or top of it's clock), the datasheet says that subsequent edges will not be recognized or generate interrupt cycles until the target cpu(s) has accepted it onto it's IRR.
Theoretically speaking then, since we are still at the beginning of our interrupt service routine dispatch, we could still run the entire IRQ chain for that line. (like when 2 pci devices share a line, we run both routines to see who needs attention.)
This leads me to believe that some edge triggered devices, could possibly malfunction if their device registers are read when it really didn't assert it's line. Is that one of the reasons?
Edge triggered line sharing
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Re: Edge triggered line sharing
If you configure the I/O APIC according to the specifications (provided by ACPI and co), none of this is really an issue.
Edge triggered (legacy devices) can't do proper interrupt sharing, nor were they designed for it. The result is that if you do get an interrupt, you'll be free to interrogate the device in question because you know it's responsible.
Secondly, for several devices, reading the IRQ register will tell you if there was a pending bit, and clear that bit the moment you read it. Therefore if you do read it, you can always respond properly, even if it wasn't from an interrupt context, so mixed reading might not even be an issue.
The only remaining problem is one of missed interrupts when you get two events before you make the time to handle them - but this is typically a programming error because it means you weren't fast enough to handle the IRQ in the first place. Also, there's nothing here that edge/level triggering fixes for you.
At the other end of the story, PCI hardware is level triggered and shared by design. Therefore hardware manufacturers should have built the I/O interface in such a fashion that querying an idle device doesn't do any harm.
Edge triggered (legacy devices) can't do proper interrupt sharing, nor were they designed for it. The result is that if you do get an interrupt, you'll be free to interrogate the device in question because you know it's responsible.
Secondly, for several devices, reading the IRQ register will tell you if there was a pending bit, and clear that bit the moment you read it. Therefore if you do read it, you can always respond properly, even if it wasn't from an interrupt context, so mixed reading might not even be an issue.
The only remaining problem is one of missed interrupts when you get two events before you make the time to handle them - but this is typically a programming error because it means you weren't fast enough to handle the IRQ in the first place. Also, there's nothing here that edge/level triggering fixes for you.
At the other end of the story, PCI hardware is level triggered and shared by design. Therefore hardware manufacturers should have built the I/O interface in such a fashion that querying an idle device doesn't do any harm.