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So far i have done a lot in my kernel, but still i haven't activated line a20. I am using bochs for testing/debugging.
I was reading about line a20 here: http://wiki.osdev.org/A20_Line
So far I have been using address space from 0x0 up to 0x9000 so I have been using only 16 bits for addressing space.
Quote from wiki:
For an operating system developer (or Bootloader developer) this means the A20 line has to be enabled so that all memory can be accessed. This started off as a simple hack but as simpler methods were added to do it, it became harder to program code that would definitely enable it and even harder to program code that would definitely disable it.
Does it mean that if NO line A20 activated and I will access more that 16 bits like 0x0001abcd (17 bits) then something will happen (like exception) ? And if A20 line activated then all would be fine, right ?
I know i can check it but i have no access to my home PC, where i keep my private files, at the moment and i can only do it in my mind, so don't be mad of asking that question
The wraparound was caused by the fact the 8086 could only access 1 megabyte of memory, but because of the segmented memory model they could effectively address up to 1 megabyte and 64 kilobytes (minus 16 bytes). Because there are twenty address lines on the 8086 (A0 through A19), any address above the 1 megabyte mark wraps around to zero. For some reason a few short-sighted programmers decided to write programs that actually used this wraparound (rather than directly addressing the memory at its normal location at the bottom of memory). Therefore in order to support these 8086-era programs on the new processors, this wraparound had to be emulated on the IBM AT and its compatibles; this was originally achieved by way of a latch that by default set the A20 line to zero. Later the 486 added the logic into the processor and introduced the A20M pin to control it.
"Certainly avoid yourself. He is a newbie and might not realize it. You'll hate his code deeply a few years down the road." - Sortie
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Intel's 286 was a badly designed piece of sh#t.
Similar to the Itanic and the P4 Netburst architecture.
Intel should have gone straight to 32bit paging, instead of implementing the retarded 286 segment protection scheme.
If Intel were smart, they would have designed the 286 as an 80186 with the 32bit page table design (same paging as 386), and included CPUID.
To access the full 4GB of address space, my design of the 286 would simply have one bit in flags determine the segment shift size. 0 = 4 bits (same as 8086), 1 = 16 bits. If flags.segment_shift = 1, DS = 0x4444 and SI = 0x8888, the calculated [DS:SI] address is 0x44448888 (not 0x4CCC8 as it would be on 8086).
The GDT, LDT, TSS and protected mode segment selectors would NOT exist in my design of the 286.
Also, the A20 mask would not be required. My 286 design (or the 386) could emulate it easily via paging.
@tom9876543: I do not think your Intel criticism is very fair although you have valid points. It was early eighties when they did what they did. Now that we see which features ended up being best, it is easy to say what they should have done at the very beginning. This is just my opinion.
Apparently Intel designed the segmented memory model of the 286, based on the "Zilog MMU".
I did a google search and came up with http://en.wikipedia.org/wiki/Zilog_Z180
From that web site it looks like the Zilog MMU is similar to the 8086. It has maximum physical address of 1MiB and there isn't protection like on the 286. So I don't know what the Intel designers were talking about. Maybe someone can find a better web reference for the Zilog MMU.
Thank you for the link to the Z8010 MMU information.
If you read the PDF, it clearly did have "protection" - the following is quoted from the PDF:
MMU memory protection-features safeguard memory areas from unauthorized or unintended access
In summary, when Intel was designing the 286, they decided to implement memory protection based on the design of the Z8010.
If Intel had brains, they would have based their design on the IBM OS/370 mainframes, which had 31bit virtual memory from 1972.
Intel could have offered 32bit virtual memory on the 286 and claimed it was superior to a mainframe </joke>
