Are the USB addresses allocated per controller or per system or per some other grouping? I wonder because I've seen USB implementations where everything that is sent seems to be sent out on each of the USB ports. In such a configuration, USB addresses would need to be per system. OTOH, logically speaking, they should be per controller.
Anybody know how this is typically implemented?
USB address allocation
- thepowersgang
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Re: USB address allocation
USB addresses are able to be per controller, but I guess some systems may do per system. On a typical system, there is only one USB2 controller, so that may be what you are seeing.
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Re: USB address allocation
On my test computer there are two controllers (at least two devices) which are attached to one USB hub each with 6 ports per hub. I have some really strange issues that seems to be related to multitasking. Each hub creates it's own thread, and then goes along to RESET and enumerate it's ports, but this malfunctions for some strange reason. It seems like it works if these processes are run in a sequence instead, because then no two devices could be in RESET state and with an 0 address at the same time. Apparently, it is the address assign command which gives a STALL back.thepowersgang wrote:USB addresses are able to be per controller, but I guess some systems may do per system. On a typical system, there is only one USB2 controller, so that may be what you are seeing.
- thepowersgang
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Re: USB address allocation
Well, addresses should be unique per controller. Because of that, only one device should be reset at once (per controller, because a reset device answers to 0 until it's told a real address).
I assume you're referring to your own USB stack here, are you sure there's two distinct controllers, and not just two ports?
I assume you're referring to your own USB stack here, are you sure there's two distinct controllers, and not just two ports?
Kernel Development, It's the brain surgery of programming.
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Acess2 OS (c) | Tifflin OS (rust) | mrustc - Rust compiler
Currently Working on: mrustc
Re: USB address allocation
At least at the PCI level, there are two devices:
Code: Select all
ACPI: .\_SB_.PCI0.EHC1, Vendor: 8086, Device: 1E26, Bus: 0, Dev: 29, Func: 0, IRQ: 23
ACPI: .\_SB_.PCI0.EHC2, Vendor: 8086, Device: 1E2D, Bus: 0, Dev: 26, Func: 0, IRQ: 16
Re: USB address allocation
I think I know what the problem is. Apparently, I try to optimize the start of the hub-ports, and thus I RESET all three permanently attached devices at the same time, creating 3 devices with a 0 address.
There must be a lock per controller that stops multiple RESETs of ports on multiple hubs or root ports at the same time.
There must be a lock per controller that stops multiple RESETs of ports on multiple hubs or root ports at the same time.