Curiosity of the 286 archictecture - question

[doxrobot]

Came across a manual for the 286, browsed through it for fun and I came across this:

The memory architecture of the Protected Mode 80286 represents a significant advance over that of the 8086. The physical address space has been increased from 1 megabyte to 16 megabytes (2^(24) bytes), while the virtual address space (i.e., the address space visible to a program) has been increased from 1 megabyte to 1 gigabyte (2^(30) bytes).

From what I know, the 286 didn't have paging, the closest you could get was maybe using not present faults to page in some data.

But afaik.. the 286 only had a 24 bit address bus, hence the 24 base in the gdt (which we will see today for backward compatibility). So without translation, our base+effective addr just goes out on the bus and would wrap at 16mb.

What is meant here by "1gb logical address space"?

[Minoto]

Chapter 6, "Virtual Memory." This chapter describes the iAPX 286 address translation mechanisms that support virtual memory. Segment descriptors, global and local descriptor tables, and descriptor caches are discussed.

[linguofreak]

What is meant here by "1gb logical address space"?

You can have a total of 16384 descriptors between the two descriptor tables. Each descriptor can describe a segment with a size up to 64 KiB. 16384*64 KiB = 1 GiB.

[doxrobot]

Makes sense now. I didn't understand the methodology behind that at first. Thanks for the info.