[SOLVED] A problem of PIT in APIC mode

[nbdd0121]

I just add I/O APIC support to my OS, and I masked all the redirection table registers in I/O APIC. However, when I removed the initializing code for 8259A, my OS catched a "double fault" (I know it is because the IRQ0 is still mapped into Vector 8, just as it is in real mode). However, I think I will not need to provide 8259A support if I support I/O APIC. What's wrong? Help meeeeeee!

[nbdd0121]

And I can't quite understand the description in IO APIC specification. I can receive a periodic singal from Interrupt Input 0, but the following description said "IRQ0 and IRQ13 interrupts are not available to the rest of the system.". Thus, I am really confused. Is the INTIN0 still the INT for PIT Timer?

Intel wrote "Interrupt Input 0: This signal is connected to the redirection table entry 0. Typically, this signal may be connected to the INTR on the PIIX3 to communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of the system." in "8093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)"

[Nable]

You should read the document "Multiprocessor specification". It's rather old but it has right schematics.
Short answer: you should mask all interrupts on 8259 + (if it's present) use IMCR register.

You can look at attached screenshots (click to open non-resized version, forum engine told me that files are too large to attach) :

[Brendan]

Hi,

I just add I/O APIC support to my OS, and I masked all the redirection table registers in I/O APIC. However, when I removed the initializing code for 8259A, my OS catched a "double fault" (I know it is because the IRQ0 is still mapped into Vector 8, just as it is in real mode). However, I think I will not need to provide 8259A support if I support I/O APIC. What's wrong? Help meeeeeee!

You can't just remove the initialisation code for the PIC chips - you have to mask all the IRQs in the PICs, and because a spurious IRQs are still possible you also have to remap the PICs (so their spurious IRQs don't cause unexpected problems). You'd also need to make sure there's no "pending IRQs" (IRQs that were received before you masked them) as these can be delivered to the CPU after they're masked.

Thus, I am really confused. Is the INTIN0 still the INT for PIT Timer?

There are "ISA IRQs" from ISA devices (PIT, floppy controller, etc) and then there are other IRQs (from PCI devices, HPET, etc). All IRQs may be connected to any IO APIC input. You can not assume that "ISA IRQs 0 to 15" are connected to "IO APIC inputs 0 to 15" - they almost never are.

To determine how ISA IRQs are mapped to IO APIC inputs you need further information from the firmware (e.g. from either the MP specification tables or ACPI tables).

Intel wrote "Interrupt Input 0: This signal is connected to the redirection table entry 0. Typically, this signal may be connected to the INTR on the PIIX3 to communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of the system." in "8093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)"

Ok, in this case they're saying that motherboard designers (who are building a motherboard that uses the PIIX3 chipset) can't use IRQ0 and IRQ13 interrupts for other pieces of hardware on their motherboard because the chipset uses them. Note: "ISA IRQ13" is used for legacy floating point error handling. For this specific chipset; I'd be tempted to guess that IO APIC input #0 is used for "external interrupt" (e.g. the PIC's INTR line) and that IO APIC input #2 is used for ISA IRQ 0.


Cheers,

Brendan

[nbdd0121]

Hi,

I just add I/O APIC support to my OS, and I masked all the redirection table registers in I/O APIC. However, when I removed the initializing code for 8259A, my OS catched a "double fault" (I know it is because the IRQ0 is still mapped into Vector 8, just as it is in real mode). However, I think I will not need to provide 8259A support if I support I/O APIC. What's wrong? Help meeeeeee!

You can't just remove the initialisation code for the PIC chips - you have to mask all the IRQs in the PICs, and because a spurious IRQs are still possible you also have to remap the PICs (so their spurious IRQs don't cause unexpected problems). You'd also need to make sure there's no "pending IRQs" (IRQs that were received before you masked them) as these can be delivered to the CPU after they're masked.

Thus, I am really confused. Is the INTIN0 still the INT for PIT Timer?

There are "ISA IRQs" from ISA devices (PIT, floppy controller, etc) and then there are other IRQs (from PCI devices, HPET, etc). All IRQs may be connected to any IO APIC input. You can not assume that "ISA IRQs 0 to 15" are connected to "IO APIC inputs 0 to 15" - they almost never are.

To determine how ISA IRQs are mapped to IO APIC inputs you need further information from the firmware (e.g. from either the MP specification tables or ACPI tables).

Intel wrote "Interrupt Input 0: This signal is connected to the redirection table entry 0. Typically, this signal may be connected to the INTR on the PIIX3 to communicate the status of IRQ0 and IRQ13 interrupts. Note that the IRQ0 and IRQ13 interrupts are embedded in the PIIX3 and are not available to the rest of the system." in "8093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)"

Ok, in this case they're saying that motherboard designers (who are building a motherboard that uses the PIIX3 chipset) can't use IRQ0 and IRQ13 interrupts for other pieces of hardware on their motherboard because the chipset uses them. Note: "ISA IRQ13" is used for legacy floating point error handling. For this specific chipset; I'd be tempted to guess that IO APIC input #0 is used for "external interrupt" (e.g. the PIC's INTR line) and that IO APIC input #2 is used for ISA IRQ 0.


Cheers,

Brendan

Thank you very much! So, I cannot assume the IRQs are from the same number of INTIN like it is in PIC?

[doxrobot]

check out 'Interrupt source override' structure in acpi for ISA to IO apic global system interrupt routing.

also afaik the PCI interrupt pin field is only relevant to the 8259 (i could be wrong) but use the PCI routing table from ACPI. It will tell you which global system interrupt corresponds to which PCI interrupt. (inta# intb#) etc.