Confusion with Intel history (Local/IO APIC question)

[Brendan]

Hi,

Thanks guys, that cleared up some of confusion for me. It's still a little bit confusing with the P6/Nahlem thing and modern CPUs, but I'll assume that from now on I have to look at Nahlem+ in the manuals not P6.

Think of it like this:

Code: Select all

8086
|__ 8088
|__ 80186
      |__ 80188

80286

80386

80486

Pentium
|__ Atom

Pentium Pro
|__ Pentium II
      |__ Pentium III
            |__ Pentium M
                  |__ Core
                        |__ Core 2
                              |__ Core i3/i5/i7 (Nehalem)
                                    |__ Core i3/i5/i7 (Sandy Bridge)
                                          |__ Core i3/i5/i7 (Ivy Bridge)

Pentium 4

Pentium Pro was the first P6, and it looks nothing like Ivy Bridge (in the same way "Linux 0.1" looks different to "Linux 3.9"). Pentium 4 was something completely different (not derived from an existing/older design), in the same way that (e.g.) iOS is different to Linux.


Cheers,

Brendan

[Mikemk]

iOS is different to Linux.

WHAT!!?
Have you ever done any hacking or modifications to iOS? At their cores, they're almost identical. Try Windows is different from Linux

[Combuster]

iOS is different to Linux.

WHAT!!?
Have you ever done any hacking or modifications to iOS? At their cores, they're almost identical. Try Windows is different from Linux

You're confusing the fact that Apple is more standards-compliant (with the help of a bunch of libraries masking the real thing) over Microsoft who just invents his own thing to force incompatibility. Architecturally Windows and Linux are closer related than iOS and either of the two.

[gusc]

Think of it like this:

Code: Select all

8086
|__ 8088
|__ 80186
      |__ 80188

80286

80386

80486

Pentium
|__ Atom

Pentium Pro
|__ Pentium II
      |__ Pentium III
            |__ Pentium M
                  |__ Core
                        |__ Core 2
                              |__ Core i3/i5/i7 (Nehalem)
                                    |__ Core i3/i5/i7 (Sandy Bridge)
                                          |__ Core i3/i5/i7 (Ivy Bridge)

Pentium 4

Aaaand the confusion is back, thanks. So, if Intel's manual says "Beginning with the Pentium 4 and Intel Xeon processors..." that means a point in the timeline (where Pentium 4 comes before Core's), right?

Are you misspelling Nehalem on purpose? Please, stop.

Sorry!

[Brendan]

Hi,

Aaaand the confusion is back, thanks. So, if Intel's manual says "Beginning with the Pentium 4 and Intel Xeon processors..." that means a point in the timeline (where Pentium 4 comes before Core's), right?

That was only a diagram of which CPU was derived from which CPU.

Chronological order is much messier. For one example, the chronological order went: 80486, Pentium, 80486DX4, Pentium Pro, Pentium MMX, then Pentium II. To make things worse, there's the marketing crud Intel use - "Celeron" and "Xeon" can mean anything anything from Pentium II to Sandy Bridge (so "Beginning with Intel Xeon processors..." could be misinterpreted as "beginning with the Pentium II Xeon released in 1998").

There's also a "logical order", which isn't really documented anywhere. It's a mixture of chronological order and "which CPU was derived from which CPU". This logical order would go like this:

Code: Select all

8086/8088
80186/80188
80286
80386
80486
80486 Overdrive (e.g. "80486DX4)
Pentium
Pentium with MMX
Pentium Pro
Pentium II
Pentium III
Pentium 4
Pentium M
Core
Core 2
Core i3/i5/i7 (Nehalem)
Core i3/i5/i7 (Sandy Bridge)
Core i3/i5/i7 (Ivy Bridge)

It's this undocumented logical order that Intel's manual is referring to.

For "Beginning with the Pentium 4 and Intel Xeon processors..." you'd assume that the "and Intel Xeon processors" part just means "Xeons based on the same Netburst micro-architecture as Pentium 4" and ignore it; then you'd take "Pentium 4 and later" from the logical order (not the chronological order) and end up with Pentium 4, Pentium M, Core, Core 2, ....


Cheers,

Brendan

[Kazinsal]

Thanks guys, that cleared up some of confusion for me. It's still a little bit confusing with the P6/Nahlem thing and modern CPUs, but I'll assume that from now on I have to look at Nahlem+ in the manuals not P6.

Are you misspelling Nehalem on purpose? Please, stop.

Making it worse is that Nehalem is the first Core i-series microarchitecture, not the first Pentium 4 microarchitecture. The Pentium 4s/Celerons waw originally of the NetBurst microarchitecture. Nehalem was originally supposed to be a tick (die shrinkage) of NetBurst but was eventually used instead as the name for the successor tock to Core (itself a successor tock to NetBurst). Thus, it is impossible for the situation postulated in the OP where Core was a crossbreed of P6 and Nehalem; Core is rather an extension of P6 through an extension of the Pentium M "Yonah" core microarchitecture.

[dozniak]

Wikipedia has a graphical representation of a part of Intel's microarchitectures list.

Here.


Some more history from ars:

By 2003, it was becoming clear that the NetBurst architecture that powered the Pentium 4 wasn't performing as well as the company had hoped—Intel had hoped to push the chips' clock speeds all the way up to 10GHz, but even at 4GHz, the Pentium 4's heat and power consumption were causing reliability problems. These same heat and power issues also made NetBurst ill-suited for use in the growing laptop segment. Rather than modify the Pentium 4's architecture to work better in laptops, the company went back to the drawing board and assigned a small team in Israel to work on a project known as Banias. This chip would later go on to be known as the Pentium M, the basis of Intel's successful Centrino marketing push (Centrino bundled a Pentium M processor, an Intel chipset, and Intel 802.11b and 802.11g wireless adapters).

Pentium M didn't start from scratch; it instead went back to Intel's Pentium III architecture and modified it to increase performance and efficiency. Pentium M also refined power saving technologies like SpeedStep, which dynamically adjusted the CPU's clock speed and voltage depending on how heavily the chip was being used.

Here