PIC or APIC?

[rubymonk]

Hello,

I'm about to setup a 32 bit IDT but before that, I have to setup the PIC.
I have an APIC present, does it mean I don't have to care about the PIC?

To my understanding, the APIC is a PIC _replacement_, which would be the PIC is not present anymore.

This being said, the intel manual states that the local APIC may be connected through LINT0 or LINT1 to a 8259 PIC.

This confuse me, should I setup the 8259 or ignore it?

Thank you.

[Combuster]

A typical computer has three distinct interrupt controllers: the PIC, the LAPIC and the IOAPIC. The LAPIC is the part of the processor itself responsible for interrupt handling, and you'll always be using it. The PIC and IOAPIC are the devices taking interrupts from devices and passing them one-by-one to the LAPIC, each over their own bus (LINT0 for the PIC and the interrupt bus for all the APIC devices: each CPU and each IOAPIC (just like the PIT, you can have more interrupt controllers to serve more devices)

The PIC system is simple and pretty much works trivially out of the box, but doesn't necessarily support support much beyond it's original share of devices. The IOAPIC is technically superior, but brings with it a load of dependencies, nor is it available on all chipsets - often missing or disabled on the singlecore era machines.

[rubymonk]

Thank you.

For a mere 32 bits initialization, I need to have the IDT setup.
For this, I need to setup the PIC, correct (AMD's manual mentions it)?

If an APIC is there, which one should I setup?
Do they cover the same functionalities?
An NMI for example will be handled by which or the 3? The PIC?

For exemple, do I need to setup the APIC for the keyboard or will the PIC handle it and the APIC actually complete the PIC by handling other devices such as USB, etc.. ?


Thanks.

[Combuster]

A typical computer has three distinct interrupt controllers: the PIC, the LAPIC and the IOAPIC. The LAPIC is the part of the processor itself responsible for interrupt handling, and you'll always be using it. The PIC and IOAPIC are the devices taking interrupts from devices and passing them one-by-one to the LAPIC, each over their own bus (LINT0 for the PIC and the interrupt bus for all the APIC devices: each CPU and each IOAPIC (just like the PIT, you can have more interrupt controllers to serve more devices)

The PIC system is simple and pretty much works trivially out of the box, but doesn't necessarily support support much beyond it's original share of devices. The IOAPIC is technically superior, but brings with it a load of dependencies, nor is it available on all chipsets - often missing or disabled on the singlecore era machines.

Please learn to read.

[rubymonk]

Okay, sorry about that.
So it means I need to init the PIC _and_ the LAPIC, right?

I see what you mean in terms of roles, I'm just unsure of what steps are necessary before I setup the IDT.


Thanks.

[Brendan]

Hi,

For a mere 32 bits initialization, I need to have the IDT setup.
For this, I need to setup the PIC, correct (AMD's manual mentions it)?

Not really.

You need an IDT (and the first 32 IDT entries) before your code can be ready to handle exceptions (and NMI); and this is typically needed very early during boot.

You also need an IDT (and whatever IDT entries) before your code can be ready for device drivers; but this typically happens much much later during boot and can be ignored until after you've got things like memory manager, scheduler, IPC, VFS, PCI bus enumeration, etc all done. Basically, you enable/setup the IRQ for a device when the device driver for that device is initialising, not before (and therefore don't need to setup PIC or IO APIC until you're starting drivers). The only IRQ you're likely to need earlier is the IRQ for whatever timer the scheduler uses, which will hopefully be the local APIC's timer (which still doesn't require PIC or IO APIC to be setup).

If an APIC is there, which one should I setup?

It's better to use the IO APIC (instead of the PIC chips) if you can.

Do they cover the same functionalities?

Both PIC and IO APIC do the same thing (control IRQs); and all devices are typically connected to both the PIC chips and the IO APIC (where whichever is enabled delivers the device's IRQ to the CPU/s). The IO APIC is much more flexible though and can correctly handle multi-CPU systems. The PIC chips are older and slower and less flexible, and don't support multi-CPU systems.

An NMI for example will be handled by which or the 3? The PIC?

NMI is typically connected to the local APIC of each CPU, but it's "special" (normal IRQs are very different).

For exemple, do I need to setup the APIC for the keyboard or will the PIC handle it and the APIC actually complete the PIC by handling other devices such as USB, etc.. ?

You don't need to setup the IO APIC or the local APIC to handle the keyboard's IRQ (you can still use the PIC chips if you want); but you should setup the IO APIC and use that for the keyboard's IRQ instead (and disable the PIC chips) because the IO APIC is better.

In theory it is possible to use the PIC chips and the IO APIC at the same time (e.g. where some IRQs are handled by PIC and others are handled by the IO APIC). In practice, it's pointless and confusing and bad (there's no sane reason to bother supporting this).


Cheers,

Brendan

[rubymonk]

Thanks a lot Brendan, this really helped me understanding.
Combuster, thanks to you too. I did read your post, just didn't get it at first. "Learn to read" even if straight to the point is a tad agressive?

Thanks to you two.