Can't write to the lapic & other issues

Anon5710 · Post by **Anon5710** » Wed Feb 20, 2013 8:36 am

Hello,

I had my IOAPIC & APIC code working on a single core platform right now i'm trying to extend that to a multicore platform.

Information that i parsed from the MADT tabels is shown below, i am 95% sure this is correct.

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4294767296 PID:0 TID:2 Global System Interrupt 1 (Pin 1) --> (IOAPIC 0x0004)IRQ 1, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 2 (Pin 2) --> (IOAPIC 0x0004)IRQ 0, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 3 (Pin 3) --> (IOAPIC 0x0004)IRQ 3, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 4 (Pin 4) --> (IOAPIC 0x0004)IRQ 4, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 5 (Pin 5) --> (IOAPIC 0x0004)IRQ 5, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 6 (Pin 6) --> (IOAPIC 0x0004)IRQ 6, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 7 (Pin 7) --> (IOAPIC 0x0004)IRQ 7, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 8 (Pin 8) --> (IOAPIC 0x0004)IRQ 8, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 9 (Pin 9) --> (IOAPIC 0x0004)IRQ 9, Level Triggerd, Active high  
4294767296 PID:0 TID:2 Global System Interrupt 10 (Pin 10) --> (IOAPIC 0x0004)IRQ 10, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 11 (Pin 11) --> (IOAPIC 0x0004)IRQ 11, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 12 (Pin 12) --> (IOAPIC 0x0004)IRQ 12, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 13 (Pin 13) --> (IOAPIC 0x0004)IRQ 13, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 14 (Pin 14) --> (IOAPIC 0x0004)IRQ 14, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 15 (Pin 15) --> (IOAPIC 0x0004)IRQ 15, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 16 (Pin 16) --> (IOAPIC 0x0004)IRQ 16, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 17 (Pin 17) --> (IOAPIC 0x0004)IRQ 17, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 18 (Pin 18) --> (IOAPIC 0x0004)IRQ 18, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 19 (Pin 19) --> (IOAPIC 0x0004)IRQ 19, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 20 (Pin 20) --> (IOAPIC 0x0004)IRQ 20, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 21 (Pin 21) --> (IOAPIC 0x0004)IRQ 21, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 22 (Pin 22) --> (IOAPIC 0x0004)IRQ 22, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 23 (Pin 23) --> (IOAPIC 0x0004)IRQ 23, Level Triggerd, Active low

Information that i found in the MADT tabels

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4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a004742c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x1
4294767296 PID:0 TID:2 	APIC ID : 0x0
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a0047434 --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x2
4294767296 PID:0 TID:2 	APIC ID : 0x1
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a004743c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x3
4294767296 PID:0 TID:2 	APIC ID : 0x2
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a0047444 --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x4
4294767296 PID:0 TID:2 	APIC ID : 0x3
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing IO APIC description table @ adress a004744c --------------------------
4294767296 PID:0 TID:2 	IO APIC ID : 0x4
4294767296 PID:0 TID:2 	IO APIC address : 0xFEC00000
4294767296 PID:0 TID:2 	Global System Interrupt Base: 0x0
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Interrupt Source Override description table @ adress a0047458 --------------------------
4294767296 PID:0 TID:2 	Bus : 0x0
4294767296 PID:0 TID:2 	Source : 0x0
4294767296 PID:0 TID:2 	Global System Interrupt: 0x2
4294767296 PID:0 TID:2 	Flags: 0x0
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Interrupt Source Override description table @ adress a0047462 --------------------------
4294767296 PID:0 TID:2 	Bus : 0x0
4294767296 PID:0 TID:2 	Source : 0x9
4294767296 PID:0 TID:2 	Global System Interrupt: 0x9
4294767296 PID:0 TID:2 	Flags: 0xD
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Local APIC NMI description table @ adress a004746c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0xFF
4294767296 PID:0 TID:2 	Flags : 0x5
4294767296 PID:0 TID:2 	Local Apic LINT# : 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------

checking if APIC is enabeld:

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MSR @ 0x1B : 0x00000000_FEE00900

information from the lapic i can acces:

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4294767296 PID:0 TID:2 ApicId : 0x00000000
4294767296 PID:0 TID:2 ApicVersion : 0x00050014
4294767296 PID:0 TID:2 TaskPrioReg : 0x00000000
4294767296 PID:0 TID:2 ArbPrioReg : 0x00000000
4294767296 PID:0 TID:2 ProcPrioReg : 0x00000000
4294767296 PID:0 TID:2 LocDestReg : 0x00000000
4294767296 PID:0 TID:2 DestFmtReg : 0xFFFFFFFF
4294767296 PID:0 TID:2 SpurIntVecReg : 0x000001FF
4294767296 PID:0 TID:2 ErrStatReg : 0x00000000
4294767296 PID:0 TID:2 IcrHigh : 0x00000000
4294767296 PID:0 TID:2 IcrLow : 0x00000200
4294767296 PID:0 TID:2 LvtTimer : 0x00010000
4294767296 PID:0 TID:2 LvtThermal : 0x00010000
4294767296 PID:0 TID:2 LvtPerfCounter : 0x00010000
4294767296 PID:0 TID:2 LvtLint0 : 0x00000700
4294767296 PID:0 TID:2 LvtLint1 : 0x00000400
4294767296 PID:0 TID:2 LvtError : 0x00010000
4294767296 PID:0 TID:2 TimerInitCount : 0x00000000
4294767296 PID:0 TID:2 TimerCurrCount : 0x00000000
4294767296 PID:0 TID:2 DivConfig : 0x00000000

To get my interrupts working, first i tried to set delivery mode to fixed and destination mode to physical and send each interrupt to the first CPU APICID = 0x00 (bits 59-56)
I tought that this would send all interrupts to the bsp cpu. But for some reason, the same code that worked on a different platform now even fails to get into my interrupt handler.
So i assume that the messages never arrived in the lapic.

Next i tried to set interrupt to fixed delivery mode and logical destination mode. Here i ran into some trouble:

My specification states that the APIC can be found at address : 0xFEE00000. My first question, What about the other 3 lapics ? (my system has 2 cores with hyper threading enabled.)
The docs also state the you can relocate each memory mapped block, but how do i do this for the other cpu's ? I have only one "MSR" to change ...... (I assume i have to switch to a different processor if i want to change their MSR ????? )

Right back to logical mode. To get this working i know i need to set DestinationFormatRegister to 0xF000FFFF and the logicalDestinationRegister to what ever i want as a logical ID
Now here is the issue, whatever i do i can't write to those registers and i do not understand why . (I did check that i wouldn't write into a read-only part of that register ---> bit-wise operators)

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g_pApic->LocDestReg |= MYPOW(31); //set bit 31 = 1
g_pApic->DestFmtReg &= 0xF0000000;

This runs wihtout a problem, but when i read those values back there are in the default state

Anyone with an idea ?

Griwes · Post by **Griwes** » Wed Feb 20, 2013 10:05 am

Anon5710 wrote:Hello,

I had my IOAPIC & APIC code working on a single core platform right now i'm trying to extend that to a multicore platform.

Information that i parsed from the MADT tabels is shown below, i am 95% sure this is correct.

Code: Select all

4294767296 PID:0 TID:2 Global System Interrupt 1 (Pin 1) --> (IOAPIC 0x0004)IRQ 1, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 2 (Pin 2) --> (IOAPIC 0x0004)IRQ 0, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 3 (Pin 3) --> (IOAPIC 0x0004)IRQ 3, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 4 (Pin 4) --> (IOAPIC 0x0004)IRQ 4, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 5 (Pin 5) --> (IOAPIC 0x0004)IRQ 5, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 6 (Pin 6) --> (IOAPIC 0x0004)IRQ 6, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 7 (Pin 7) --> (IOAPIC 0x0004)IRQ 7, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 8 (Pin 8) --> (IOAPIC 0x0004)IRQ 8, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 9 (Pin 9) --> (IOAPIC 0x0004)IRQ 9, Level Triggerd, Active high  
4294767296 PID:0 TID:2 Global System Interrupt 10 (Pin 10) --> (IOAPIC 0x0004)IRQ 10, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 11 (Pin 11) --> (IOAPIC 0x0004)IRQ 11, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 12 (Pin 12) --> (IOAPIC 0x0004)IRQ 12, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 13 (Pin 13) --> (IOAPIC 0x0004)IRQ 13, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 14 (Pin 14) --> (IOAPIC 0x0004)IRQ 14, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 15 (Pin 15) --> (IOAPIC 0x0004)IRQ 15, Edge Triggerd, Active high 
4294767296 PID:0 TID:2 Global System Interrupt 16 (Pin 16) --> (IOAPIC 0x0004)IRQ 16, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 17 (Pin 17) --> (IOAPIC 0x0004)IRQ 17, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 18 (Pin 18) --> (IOAPIC 0x0004)IRQ 18, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 19 (Pin 19) --> (IOAPIC 0x0004)IRQ 19, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 20 (Pin 20) --> (IOAPIC 0x0004)IRQ 20, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 21 (Pin 21) --> (IOAPIC 0x0004)IRQ 21, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 22 (Pin 22) --> (IOAPIC 0x0004)IRQ 22, Level Triggerd, Active low  
4294767296 PID:0 TID:2 Global System Interrupt 23 (Pin 23) --> (IOAPIC 0x0004)IRQ 23, Level Triggerd, Active low

GSI#2 -> IRQ0 seems right, but you missed GIS#1.

Information that i found in the MADT tabels

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4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a004742c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x1
4294767296 PID:0 TID:2 	APIC ID : 0x0
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a0047434 --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x2
4294767296 PID:0 TID:2 	APIC ID : 0x1
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a004743c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x3
4294767296 PID:0 TID:2 	APIC ID : 0x2
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Processor Local APIC description table @ adress a0047444 --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0x4
4294767296 PID:0 TID:2 	APIC ID : 0x3
4294767296 PID:0 TID:2 	Flags: 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing IO APIC description table @ adress a004744c --------------------------
4294767296 PID:0 TID:2 	IO APIC ID : 0x4
4294767296 PID:0 TID:2 	IO APIC address : 0xFEC00000
4294767296 PID:0 TID:2 	Global System Interrupt Base: 0x0
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Interrupt Source Override description table @ adress a0047458 --------------------------
4294767296 PID:0 TID:2 	Bus : 0x0
4294767296 PID:0 TID:2 	Source : 0x0
4294767296 PID:0 TID:2 	Global System Interrupt: 0x2
4294767296 PID:0 TID:2 	Flags: 0x0
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Interrupt Source Override description table @ adress a0047462 --------------------------
4294767296 PID:0 TID:2 	Bus : 0x0
4294767296 PID:0 TID:2 	Source : 0x9
4294767296 PID:0 TID:2 	Global System Interrupt: 0x9
4294767296 PID:0 TID:2 	Flags: 0xD
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------
4294767296 PID:0 TID:2 -------------------Printing Local APIC NMI description table @ adress a004746c --------------------------
4294767296 PID:0 TID:2 	ACPI Processor ID : 0xFF
4294767296 PID:0 TID:2 	Flags : 0x5
4294767296 PID:0 TID:2 	Local Apic LINT# : 0x1
4294767296 PID:0 TID:2 ------------------------------------------------------------------------------------------

Looks sane.

My specification states that the APIC can be found at address : 0xFEE00000. My first question, What about the other 3 lapics ? (my system has 2 cores with hyper threading enabled.)
The docs also state the you can relocate each memory mapped block, but how do i do this for the other cpu's ? I have only one "MSR" to change ...... (I assume i have to switch to a different processor if i want to change their MSR ????? )

Each LAPIC is "local", that is, accessible only from its core. The answer to address question - every LAPIC is at 0xFEE00000. To change other's CPU MSR, you have to boot it and execute code on it.

Right back to logical mode. To get this working i know i need to set DestinationFormatRegister to 0xF000FFFF and the logicalDestinationRegister to what ever i want as a logical ID
Now here is the issue, whatever i do i can't write to those registers and i do not understand why . (I did check that i wouldn't write into a read-only part of that register ---> bit-wise operators)
Code: Select all
g_pApic->LocDestReg |= MYPOW(31); //set bit 31 = 1
g_pApic->DestFmtReg &= 0xF0000000;
This runs wihtout a problem, but when i read those values back there are in the default state

Anyone with an idea ?

How are LocDestReg and DestFmtReg defined (I guess they are not volatile)? Also, 0xF000FFFF is not a valid value for DFR, neither according to Intel manual, nor AMD one. Intel says that 28 lower bits must be set, AMD that they must be zero. And although the mention of 0xF000FFFF is wrong, the code seems sane.

Anon5710 · Post by **Anon5710** » Wed Feb 20, 2013 10:57 am

but you missed GIS#1.

What do you mean by that ?

i memory map my register like this :

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g_pApic = (volatile APIC_REGS *)OALCAtoUA( NKCreateStaticMapping (APIC_REGS_PHYS_BASE>>8, sizeof (APIC_REGS)));
g_pApic->LocDestReg |= MYPOW(31); //set logical apic ID for core1 to 10000000b
g_pApic->DestFmtReg &= 0xF0000000;

I'm not really sure about the OALCATOUA() macro but suppos edly this should move cached memory to uncached memory. See http://msdn.microsoft.com/en-us/library/ee478817.aspx
(I know that this is pretty old code from Microsoft, writing something to test that)

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//write to one lapic register
	DWORD DestFmtReg = 0xFEE000E0;
	pdwSize = 4;
	volatile DWORD *lapic_format = (volatile DWORD*)OALCAtoUA(PhysicalAddressToVirtual(DestFmtReg, &pdwSize));
	OALMSG(TRUE , (L"Lapic format register @ adress 0x%08X: 0x%08X \r\n",*lapic_format,lapic_format));
	*lapic_format &= 0xF0000000;
	OALMSG(TRUE , (L"Lapic format register @ adress 0x%08X: 0x%08X \r\n",*lapic_format,lapic_format));


	//write to one lapic register
	DestFmtReg = 0xFEE000E0;
	pdwSize = 4;
	lapic_format = (volatile DWORD*)PhysicalAddressToVirtual(DestFmtReg, &pdwSize);
	OALMSG(TRUE , (L"Lapic format register @ adress 0x%08X: 0x%08X \r\n",*lapic_format,lapic_format));
	*lapic_format &= 0xF0000000;
	OALMSG(TRUE , (L"Lapic format register @ adress 0x%08X: 0x%08X \r\n",*lapic_format,lapic_format));

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4294767296 PID:0 TID:2 Lapic format register @ adress 0xFFFFFFFF: 0xA00C00E0 
4294767296 PID:0 TID:2 Lapic format register @ adress 0xFFFFFFFF: 0xA00C00E0 
4294767296 PID:0 TID:2 Lapic format register @ adress 0xFFFFFFFF: 0xA00C00E0 
4294767296 PID:0 TID:2 Lapic format register @ adress 0xFFFFFFFF: 0xA00C00E0

Seems legit : http://msdn.microsoft.com/en-us/library/ee479209.aspx

So basicly my variable is volatile and uncached....

Last, 0xF000FFFF was a mistype

Griwes · Post by **Griwes** » Wed Feb 20, 2013 11:42 am

Argh, that was supposed to be "you missed GIS#0", since interrupt sources are numbered from 0 to `size - 1`.

Anon5710 · Post by **Anon5710** » Wed Feb 20, 2013 11:59 am

Thats because, IRQ2 is remapped as the RTC IRQ source

And IRQ2 is normally used to link one 8259 to another 8259

Griwes · Post by **Griwes** » Wed Feb 20, 2013 12:39 pm

No, IRQ0 (PIT) is remapped to IOAPIC input #2, not the other way around. Still, you cannot paste data for 23 of (probably) 24 IOAPIC inputs and ask if it's 100% right.

Also, why are you using some weird MS functions/macros/whatever you don't even understand? What kind of software are we even talking about?

Anon5710 · Post by **Anon5710** » Thu Feb 21, 2013 3:08 am

I'm a junior software developer and my current job is to write the apic code for windows compact 7

Even if this site is dedicated to osdeving, this is still one of the best places to get information about pc hardware

Jezze · Post by **Jezze** » Thu Feb 21, 2013 6:15 am

So many questions...

1. Why don't they reuse the code from normal Windows? Is it bloated?
2. Why do they put a junior programmer on that task? (if junior means like almost straight out of school)
3. Why work on Windows to begin with? Adopt Linux for christ sake.

Anon5710 · Post by **Anon5710** » Thu Feb 21, 2013 7:17 am

Alright, I'm able to write to my register now, i had a offset of 1 byte wrong ( :/ )

I do have a few extra questions.

I'm working with an intel atom N2000 series (dualcore + hyperthreading) CPU, the APIC datasheets specify 2 classes where interrupt handling is different.
I suppose my cpu is closer to the P6 family and Pentium family of processors than(or then ?) the Pentium 4, Intel Xeon family ?

Right now i'm trying implement apic interrupts with :
Fixed interrupts and logical destination mode in the flat model

This means i have to program the redirection entries in IOAPIC to use logical dest mode, and program bits 63-56 to specify the logical destination address of a set of processors. (and other settings where i am 99% sure of

)
Whenever a APIC receives an IPI message which specifies an message destination address (MDA). On this MDA and the logical APIC id a bit-wise AND is performed and whenever a TRUE condition is detected the IPI is accepted.

First, i assume that the MDA is the same as the address i specified in bits 63-56 for each redirection entry (in the IOAPIC), right ?

Second, i'm a bit confused by this text out of the datasheet.

Flat Model — This model is selected by programming DFR bits 28 through 31 to 1111. Here, a unique logical
APIC ID can be established for up to 8 local APICs by setting a different bit in the logical APIC ID field of the LDR
for each local APIC. A group of local APICs can then be selected by setting one or more bits in the MDA.

Does this mean that i am obligated to set a different logical id for each cpu core ? Because right now, i only configured my BSP to match the logical address in the MDA and the other 3 are probably still set to the default state.

Regards Anon5710

Anon5710 · Post by **Anon5710** » Thu Feb 21, 2013 7:29 am

Jezze wrote:So many questions...

1. Why don't they reuse the code from normal Windows? Is it bloated?
2. Why do they put a junior programmer on that task? (if junior means like almost straight out of school)
3. Why work on Windows to begin with? Adopt Linux for christ sake.

1) Windows compact is a subset of "normal windows" and for most parts the source code is given to me. Unfortunately the APIC is not supported in windows compact 7, so i'm writing that code

2) I'ts true that i came straight from school, however i am an engineer. I am perfectly capable to get this working (I'aint asking for code, just information

)
3) Support, you try finding a company that sells a RealtimeOS that isn't going to dissapear in the next few years and has good tech support. (Thats what they told me

)

Combuster · Post by **Combuster** » Thu Feb 21, 2013 8:41 am

Anon5710 wrote:3) Support, you try finding a company that sells a RealtimeOS that isn't going to dissapear in the next few years and has good tech support.

Of course, the competition is always deemed worse, even though it gets used everywhere.

Anon5710 · Post by **Anon5710** » Thu Feb 21, 2013 8:50 am

I tend to agree with you, but i don't think my company would like to rewrite all the software designed for windows compact

Brendan · Post by **Brendan** » Thu Feb 21, 2013 9:19 am

Hi,

Anon5710 wrote:First, i assume that the MDA is the same as the address i specified in bits 63-56 for each redirection entry (in the IOAPIC), right ?

Yes.

Anon5710 wrote:Second, i'm a bit confused by this text out of the datasheet.

Flat Model — This model is selected by programming DFR bits 28 through 31 to 1111. Here, a unique logical
APIC ID can be established for up to 8 local APICs by setting a different bit in the logical APIC ID field of the LDR
for each local APIC. A group of local APICs can then be selected by setting one or more bits in the MDA.
Does this mean that i am obligated to set a different logical id for each cpu core ?

You're not obligated ("can" vs. "shall" or "must") - you can use those 8 bits for anything you like. For example, you might have 26 logical CPUs and decide to use 11 of them for counting chickens, and then use bit 5 of the MDA for "CPUs being used to count chickens" so that you can broadcast an IPI to all the chicken counting CPUs.

The only real restriction is that you shouldn't send an IPI to nothing (e.g. if no CPU has bit 7 set in its LDR, then sending an interrupt with logical destination and MDA set to 0x80 will cause problems because none of the CPUs are able to accept it). This means that if you haven't set any bits in the LDR of any AP CPUs then the only CPU that can accept an IPI that uses logical destination would be the BSP; and you should probably just use fixed delivery to send to the BSP instead of bothering with logical destinations.

Cheers,

Brendan

Anon5710 · Post by **Anon5710** » Thu Feb 21, 2013 9:47 am

Hi brendan,

This means that if you haven't set any bits in the LDR of any AP CPUs then the only CPU that can accept an IPI that uses logical destination would be the BSP; and you should probably just use fixed delivery to send to the BSP instead of bothering with logical destinations.

Well, that's what i first tried to do. I can get physical destination mode and logical destination mode working on my single core platform.
Unfortunately neither works when a a multiprocessor comes into play. It never reaches my interrupt handler. I don't even think any lapic accepts those ipi message

Do you have an idea what could cause this ?
Honestly i'm thinking that the MPSupport lib provided by windows compact isn't "complete".

OSDev.org

Can't write to the lapic & other issues

Can't write to the lapic & other issues

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Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues

Re: Can't write to the lapic & other issues