How does the LAPIC accepts an I/O APIC interrupt?

[limp]

Hi all,

I am trying to figure out the way the LAPIC accepts an I/O APIC interrupt. From the Intel manuals, on the top of the "Interrupt Acceptance Flow Chart for the Local APIC" it is mentioned that the APIC waits to Receive a Bus Message ("Wait to Receive Bus Message" state).

Does anyone know if that wait means that the APIC will poll the system bus for detecting a bus message or the bus message will interrupt the LAPIC?

Thanks in advance.

[sounds]

Hi all,

I am trying to figure out the way the LAPIC accepts an I/O APIC interrupt. From the Intel manuals, on the top of the "Interrupt Acceptance Flow Chart for the Local APIC" it is mentioned that the APIC waits to Receive a Bus Message ("Wait to Receive Bus Message" state).

Does anyone know if that wait means that the APIC will poll the system bus for detecting a bus message or the bus message will interrupt the LAPIC?

Thanks in advance.

The bus message will interrupt the LAPIC. The LAPIC does not poll the bus. The LAPIC also does not have to accept the message the first time it is sent from the I/O APIC.

I can't quite understand your question, so I'll briefly explain:

The bus referred to in the Intel manuals is the APIC bus, which is a dedicated bus just for APICs (and I/O APICs). In other words, the interrupt will not come in over the regular bus that handles memory and I/O accesses. One downside to sending an interrupt over a dedicated bus is that there is no way to be sure all the memory transactions finished (e.g. the netword card is receiving a packet) in-order before the interrupt is asserted in the CPU. This example would mean the network card driver must first find a way to ensure memory is "coherent" (transactions have all completed) before trying to process the data.

The next version of interrupts uses "MSI" where the interrupt comes in over the regular memory and I/O bus - which means the driver does not have to make sure memory is coherent.

Please read up on some of the terms I've mentioned, for example this is a good starting point:

http://en.wikipedia.org/wiki/Intel_APIC_Architecture

[limp]

The bus referred to in the Intel manuals is the APIC bus, which is a dedicated bus just for APICs (and I/O APICs). In other words, the interrupt will not come in over the regular bus that handles memory and I/O accesses.

You probably refer to older versions of the APIC architecture (for P6 processors and Pentium CPUs) as in the newer APIC architecture version the I/O APIC send the interrupts (via bridge H/W) to the LAPIC over the system bus. I guess that by system bus they mean FSB.

[sounds]

You probably refer to older versions of the APIC architecture (for P6 processors and Pentium CPUs) as in the newer APIC architecture version the I/O APIC send the interrupts (via bridge H/W) to the LAPIC over the system bus. I guess that by system bus they mean FSB.

Not exactly, but sure, newer systems only emulate the original APIC architecture, including the problems with coherency. What was it you wanted to know?