SATA SCR registers: the purpose and applicability

[jacks]

Hi all,

While mangling through ata and sata docs, I came through the term sata control registers or SCRs. I have some questions about them, as till now I didn't find any concrete info about them(except sata spec which does describe them, but I'm concerned with their practical usage. ).

Q1. Where are they implemented - in sata drive itself or in sata host bus adapter(hba)? It seems they are implemented in HBA itself.

Q2. Suppose pci sata controller is in PCI IDE native mode, do we need to conside SCRs, while communicating with sata drives?

Q3. Are SCRs valid only in non-ahci mode(ie valid only in pci ide native mode)?

Q4. Are SCRs really standarized? ie do SCR registers are present on every sata hba(though they can be in different location in pci configuration space.)?

Q5. While communicating with sata drives via a sata hba in pci ide native mode, is SRST(software reset bit) is just a dummy bit? Should we use SCR registers somehow to actually reset sata drives, even in pci ide native mode? ATA docs, say that after setting SRST bit, we must reset this bit as it will not be reset by hardware. Is this true for SATA HBAs (in pci ide native mode) too?

Are there any other sata specific registers(like SCRs) that need to be considered while communicating with sata drives via a sata hba in pci ide native mode?

Update on 2012-09-06:

The sata specification does mention about SCRs, in section 10.1.

It also states that these registers are associated with serial interface and are independent of any master/slave emulation the host adapter may implement.

It seems that even in pci ide native mode we need to deal with SCRs. Am I right?

I updated the original question accordingly.

Thanks!