Interrupt handling and tss

[tomasbrod]

My code is running in ring 2. Interrupt from keyboard or timer arrives. There is a interrupt gate on IDT that points to kernel code to ring 0. CPU loads sp and ss from tss becose the dpl switch. I have only one TSS. And my question is: Where goes the old values of ss and sp? I want to use and restore them.

[bluemoon]

From the manual 6.12:

If the handler procedure is going to be executed at a numerically lower privilege level, a stack switch occurs. When the stack switch occurs:
a. The segment selector and stack pointer for the stack to be used by the handler are obtained from the TSS for the currently executing task. On this new stack, the processor pushes the stack segment selector and stack pointer of the interrupted procedure.

So, when stack switch the old SS:E/RSP is pushed on ring0 stack, it's usually restored with IRET when the handler exit.

[tomasbrod]

So the stack state at begin of the handler is:
SS
SP
FLAGS
CS
IP
--TOP--
How CPU knows that there is stack segment and pointer on the stack? Eg: Kernel is running. Interrupt arruves DPL switch will not occur so SS SP is not on stack and handler does a IRET. I cannot find the IRET instruction in manual.

[jbemmel]

My guess would be it looks at the RPL in the CS selector found on the stack, if != current then it assumes SS and ESP are also there

[bluemoon]

DO NOT GUESS. I suggest you check IRET with the manual, the behavior of the instruction is well documented.

PS. Instructions are listed on volume2, if you got a decent computer I recommend to download the 1+2+3 combo.

[tomasbrod]

Thank you. I was looking
RETI instruction. Now i understand privilege level switch. Unluckyly getting 3rd exception in some other code.
How can i mark this thread solved, or dont reply if it is not necessary.
Thank you a lot.

[qw]

How can i mark this thread solved

Edit the original post and change the subject line.

[egos]

My code is running in ring 2.

Why?

I have only one TSS.

And what about handling kernel panic? I have two additional TSSes. One (per core) for handling kernel panic (kernel stack overflow). And one (per system) for NMI handling.