How to shutdown the PIT

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AlfaOmega08
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How to shutdown the PIT

Post by AlfaOmega08 »

I know this might look quite strange to read, after all the problems that someone has to enable the PIT, I want it to STOP! I'm going to use the HPET and I don't want the PIT to interfere. I can't just mask IRQs on the PIC and/or I/O APIC because that same IRQs might be used by the HPET itself. So how would you do this?

I tought to use one-shot mode for a very short period and then never touch it anymore, but that would trigger an IRQ right? Isn't there any "interrupt-free" way?

Thanks
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turdus
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Re: How to shutdown the PIT

Post by turdus »

Simply mask it, should be enough. If not, then configure it in one-shot mode and never reset it's counter.
jnc100
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Re: How to shutdown the PIT

Post by jnc100 »

In standard mode, you can configure which IRQ is triggered when the various HPET timers fire. Alternatively if it is programmed in legacy replacement mode then the PIT is disabled from sending interrupts and HPET timer 0 is routed to IRQ 0 on the PIC and IRQ 2 on the IOAPIC, with HPET timer 1 routed to IRQ 8 on both.

Regards,
John.
LindusSystem
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Re: How to shutdown the PIT

Post by LindusSystem »

Just mask the IRQ 0 in the PIC and done, you wont receive any interrupt 0s but what make you shutdown the PIT?
Anyone has a idea of making a ntfs bootsector?if yes PM me , plz.
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serviper
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Re: How to shutdown the PIT

Post by serviper »

One-shot-mode should be enough to stop the timer - If you do not reload the counter, PIT won't counting on.
However, PIT is always connected to PIC on a PC so there's hardly an interrupt-free solution, I think.
LindusSystem
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Re: How to shutdown the PIT

Post by LindusSystem »

Still I want to know why you want to shutdown the PIT because you will need it for Process Scheduling,etc as using RTC will not be accurate.
Anyone has a idea of making a ntfs bootsector?if yes PM me , plz.
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Nessphoro
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Re: How to shutdown the PIT

Post by Nessphoro »

From the HPET specification:
If the Legacy Replacement Route bit (LEG_RT_CNF) is set (‘1’), the following mapping is forced:
Timer 0: 8259 Mapping - IRQ0, APIC Mapping - IRQ2 ( In this case, the 8254 timer will not cause any interrupts)
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