Timer related problems

[avenger]

Hi all,
I have some firmware that I want to run. But, unfortunately, there is no original loader for it. So I decided to write my own wrapper (lets say loaded via BIOS) that would make required initialization and load/start firmware.
I solved problems of loading firmware, setting up GDT/IDT and starting firmware. But faced problems inside firmware itself, that are caused of missing initialization I think.

This some sort of timer calibration loop (or something like this):

Code: Select all

xor     ecx, ecx
xor     ebx, ebx
jmp     short loop1_entry

loop1:
inc     ecx

loop1_entry:
mov     edx, 20h
in      al, dx
test    al, 1
jz      short loop1

mov     eax, 80h
mov     dl, 61h
out     dx, al
jmp     short loop2_entry

loop2:
inc     ecx

loop2_entry:
mov     edx, 20h
in      al, dx
test    al, 1
jnz     short loop2

inc     ebx
cmp     ebx, 99
jle     short loop1_entry

mov     dx, 10000
lea     eax, [ecx+5000]
mov     ecx, edx
xor     edx, edx
div     ecx

Before this piece of code timer initialized to 1000Hz, square wave, channel 0.
Currently if we disable interrupts (cli) - this code will loop at loop2 forever. If I put empty IRQ0 handler and enable interrupts - then this code will loop forever on loop1 (because my handler just 'out 0x20, 0x20' - so IRQ0 marked as serviced, and read from 0x20 port will return bit0=0)
I suspect that IRQ0 handler and whole system should be somehow dependent on 'out 0x80, 0x61'. So the IRQ will be serviced only after this command block.
But in Intel ICHx documentation this mostly a read-only port

One thing that I found, that could be related to operation:

Port 061 - 8255A-5 Port B

1xxx xxxx 0=Keyboard enable, 1=Keyboard acknowledge
PS/2: Write: Reset Timer 0 Output Latch (IRQ0)
Read: Parity check (1=parity check occured).

So writing 0x80 to 0x61 should "Reset Timer 0 Output Latch"... But I have no clue how system and handler should be initialized to honor this operation.

If someone had seen such code before - please help to understand.

[avenger]

Seems that I understood what that code does.
It waits 1/10 of second without any IRQ0 handlers required, but acknowledges IRQ receiving by resetting it (outb 0x80, 0x61). This seems to be right behavior on PS/2 compatible systems.
But I was testing all this on QEMU - where port 0x61 is solely for PC Speaker, so it was ignoring everything except bit1 in this port.