I read on the wiki that it could fire for a few different reasons, so I pulled up my intel manual. Sadly, my manual says that the Single Step/Debug exception (vector 1) is reserved.
Can someone give me some more information on when and why the Debug exception occurs?
Edit:
Found some more information on the debug registers. This page is helpful: http://www.logix.cz/michal/doc/i386/chp12-02.htm
I check DR6, bits 13-15. Bit 14 was set, and according to that page, this means it was a result of Trap Flag being set in EFLAGS, but I never set TF... I setup EFLAGS like so:
Code: Select all
newreg->eflags = 0x102; // (IF | IOPL=0)
Is it safe to just ignore the debug exception? According to the wiki, it could be a fault, but I can't find documentation on how to determine that.