I am developing a 64-bit OS.I wanted to implement multiprocessing but where will the Local and I\O APIC be?
I have read the Intel documents for it's 32-bit APICs,but in 64-bit mode it is the same or it is different?
Where is the Local APIC in Long Mode?
- amd64pager
- Member
- Posts: 73
- Joined: Fri Nov 25, 2011 8:27 am
- Location: In the 266 squadron of the RFC,near Maranique in the Southern Front in the WW1
Where is the Local APIC in Long Mode?
It's surprising what the semiconductor industry's definition of macro is and what the CS description is.
Re: Where is the Local APIC in Long Mode?
it will be in same location, usually
- Local APIC: FEE0 0000h
- I/O APIC: FEC0 0000h
I Love Life because Life Loves Me!
- amd64pager
- Member
- Posts: 73
- Joined: Fri Nov 25, 2011 8:27 am
- Location: In the 266 squadron of the RFC,near Maranique in the Southern Front in the WW1
Re: Where is the Local APIC in Long Mode?
Thanks for the reply.
The Local APIC has pointers to ISRs(Interrupt Service Routines), but will that still be 32-bit or will it be extended?
You can include references to the AMD64 Architecture Programmers Guide Volume 2.
The Local APIC has pointers to ISRs(Interrupt Service Routines), but will that still be 32-bit or will it be extended?
You can include references to the AMD64 Architecture Programmers Guide Volume 2.
It's surprising what the semiconductor industry's definition of macro is and what the CS description is.
Re: Where is the Local APIC in Long Mode?
I think you've misunderstood something
Local APIC isn't related to ISRs
IDT (Interrupt Descriptor Table) it contains pointers to ISRs and IDT structure changes in long mode so it can contain 64-bit pointers
IDTR specifies size and location to IDT
I haven't read AMD manuals, just Intel (because all my PCs have only Intel CPUs)
anyway:
Local APIC isn't related to ISRs
IDT (Interrupt Descriptor Table) it contains pointers to ISRs and IDT structure changes in long mode so it can contain 64-bit pointers
IDTR specifies size and location to IDT
I haven't read AMD manuals, just Intel (because all my PCs have only Intel CPUs)
anyway:
- 82093AA I/O ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (IOAPIC)
- Chapter 6 (INTERRUPT AND EXCEPTION HANDLING)
and 10 (ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)) in Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1 - Chapter 5.2.12 (Multiple APIC Description Table (MADT)) in Advanced Configuration and Power Interface Specification (Revision 4.0a)
I Love Life because Life Loves Me!
- amd64pager
- Member
- Posts: 73
- Joined: Fri Nov 25, 2011 8:27 am
- Location: In the 266 squadron of the RFC,near Maranique in the Southern Front in the WW1
Re: Where is the Local APIC in Long Mode?
Thanks for that reply also.
So I\O APIC and Local APICs are the same in long mode.
So I\O APIC and Local APICs are the same in long mode.
It's surprising what the semiconductor industry's definition of macro is and what the CS description is.
Re: Where is the Local APIC in Long Mode?
Ask the cpu to tell it's local apic address. It's in MSR 1Bh, and it's a 64 bit address.