[SPARC64] Memory address translation under UltraSPARC IIIi

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aod
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[SPARC64] Memory address translation under UltraSPARC IIIi

Post by aod »

Hello!
I seek for help in understanding how to manage virtual address translation under SPARC architecture. I've read SPARC V9 Architecture Manual and UltraSPARC IIIi User's Guide, but I can't find anything.
How is this translation done? How to setup ASIs?
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Combuster
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Re: [SPARC64] Memory address translation under UltraSPARC II

Post by Combuster »

SPARC is designed as an architecture, and not as a chip. Processors don't need to implement a MMU so you'll have to find the manual for the processor you're targeting instead to find out how the MMU is implemented.
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aod
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Re: [SPARC64] Memory address translation under UltraSPARC II

Post by aod »

Yes, I know, I've read the User's Manual of my processor, but data I've found are insufficient to program operating system. There is only little information about virtual memory and nothing about translation maps.
EDIT: apparently, MMU documentation is not publicly available: http://kerneltrap.org/node/568
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