Hi!
I decided to use VBE as GUI for my OS but have a problem. VESA resolutions are stretched on my screen so I would need to patch video mode with new values (1366x768) as is done in 915resolutions. The problem is that i5 (HM55 chipset) does not have the same PAM registers as older chipsets to unlock C0000 space.
I tried with MTRR to set it all options except read-only but I still cannot change anything in video bios region.
Any hints would be welcome..
BR,
iostres
Patching VESA videomodes - i5
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Re: Patching VESA videomodes - i5
Well, the logical solutions are either
1) Write a native driver so you can actually get the monitor's information and set an appropriate mode without bios limitations.
2) Get the specifications for the new chipset and find the new memory controller register responsible for the C0000-FFFFF locks. MTRRs should not physically govern writability of memory addresses, that's the memory controller's task.
1) Write a native driver so you can actually get the monitor's information and set an appropriate mode without bios limitations.
2) Get the specifications for the new chipset and find the new memory controller register responsible for the C0000-FFFFF locks. MTRRs should not physically govern writability of memory addresses, that's the memory controller's task.
Re: Patching VESA videomodes - i5
This is the excerpt from HM55 documentation:
PAM (000C_0000h-000F_FFFFh)
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area. Each section has Read enable and Write enable attributes. The CPU documentation will now contain the registers and decode rules/restrictions.
The PAM registers have moved to the CPU. For the PAM register details, refer to CPU documentation.
• ISA Expansion Area (000C_0000h-000D_FFFFh)
• Extended System BIOS Area (000E_0000h-000E_FFFFh)
• System BIOS Area (000F_0000h-000F_FFFFh)
The CPU contains the PAM registers and the GMCH has no knowledge of the register programming. The CPU decodes the request and routes to the appropriate destination (DRAM or DMI) by sending the request on HOM or NCS/NCB.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Graphics translated requests to this region are not allowed. If such a mapping error occurs, the request is routed to 000C_0000h. Writes will have the byte enables de-asserted.
But I am unable to find PAM's in CPU documentation
PAM (000C_0000h-000F_FFFFh)
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area. Each section has Read enable and Write enable attributes. The CPU documentation will now contain the registers and decode rules/restrictions.
The PAM registers have moved to the CPU. For the PAM register details, refer to CPU documentation.
• ISA Expansion Area (000C_0000h-000D_FFFFh)
• Extended System BIOS Area (000E_0000h-000E_FFFFh)
• System BIOS Area (000F_0000h-000F_FFFFh)
The CPU contains the PAM registers and the GMCH has no knowledge of the register programming. The CPU decodes the request and routes to the appropriate destination (DRAM or DMI) by sending the request on HOM or NCS/NCB.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM. Graphics translated requests to this region are not allowed. If such a mapping error occurs, the request is routed to 000C_0000h. Writes will have the byte enables de-asserted.
But I am unable to find PAM's in CPU documentation
Re: Patching VESA videomodes - i5
You need the relevant datasheet for your particular processor. For example 2nd generation desktop core datasheet.
Regards,
John.
Regards,
John.