Connectivity of I/O APIC with the processor

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limp
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Connectivity of I/O APIC with the processor

Post by limp »

Hi guys,

I've got some questions regarding the connectivity of the I/O APIC with the processor. I found out that for processors produced after the production of Pentium 4 and Intel Xeon ones, the I/O APIC is connected over the system bus rather than over the 3-wire-inter-APIC bus as it used to be. Also, it is also showed that in these newer processors, the I/O APIC is connected into the PCI bus which in turn is connected to the CPU bus through a PCI bridge.

Now, by looking at ICH7 datasheet it is mentioned that the ICH7’s PCI-to-PCI bridge connects the DMI to the PCI bus.

I've got two questions:
1) Is the ICH7’s PCI-to-PCI bridge the same PCI bridge refereed in the Intel Devel. Manuals used for connecting the I/O APIC to the CPU bus (See the "ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)" chapter)?

2) Are both the PCI bridge and the Northbridge connected to the CPU bus? I thought that only the Northbridge was connected to the CPU bus but obviously I was wrong?

Thanks in advance.
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Combuster
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Re: Connectivity of I/O APIC with the processor

Post by Combuster »

2) Are both the PCI bridge and the Northbridge connected to the CPU bus? I thought that only the Northbridge was connected to the CPU bus but obviously I was wrong?
DMI is the name for the physical link between Northbridge (MCH) and Southbridge (ICH). Since hardware wants to stay compatible to older system with their PCI configuration protocols, Northbridge pretends to be the Host-to-PCI bridge (and a bunch of PCI-to-PCI bridges connected behind it that actually do PCI express). This "fake" PCI bus is tunneled over the DMI where the southbridge adds another "PCI-to-PCI" bridge of its own make, as well as actually connecting the PCI bus itself. Probably, the interrupt controller is not actually connected to a PCI bus at all as it's built into a chip that's mostly designed to be a big switchboard.

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