list of invalid x86 instructions in 64bit long mode
list of invalid x86 instructions in 64bit long mode
any body has the list of invalid x86 instructions in 64bit long mode?
I'm using AMD Sempron 140 Single core 2.7GHz
Re: list of invalid x86 instructions in 64bit long mode
i found in AMD manual vol3 appendix b-3:
B.3 Invalid and Reassigned Instructions in 64-Bit Mode
Table B-2 lists instructions that are illegal in 64-bit mode. Attempted use of these instructions
generates an invalid-opcode exception (#UD).
Table B-2. Invalid Instructions in 64-Bit Mode
AAA ---------- 37 ASCII Adjust After Addition
AAD ---------- D5 ASCII Adjust Before Division
AAM ---------- D4 ASCII Adjust After Multiply
AAS ---------- 3F ASCII Adjust After Subtraction
BOUND ---------- 62 Check Array Bounds
CALL (far) ---------- 9A Procedure Call Far (far absolute)
DAA ---------- 27 Decimal Adjust after Addition
DAS ---------- 2F Decimal Adjust after Subtraction
INTO ---------- CE Interrupt to Overflow Vector
JMP (far) ---------- EA Jump Far (absolute)
LDS ---------- C5 Load DS Far Pointer
LES ---------- C4 Load ES Far Pointer
POP DS ---------- 1F Pop Stack into DS Segment
POP ES ---------- 07 Pop Stack into ES Segment
POP SS ---------- 17 Pop Stack into SS Segment
POPA, POPAD ---------- 61 Pop All to GPR Words or Doublewords
PUSH CS ---------- 0E Push CS Segment Selector onto Stack
PUSH DS ---------- 1E Push DS Segment Selector onto Stack
PUSH ES ---------- 06 Push ES Segment Selector onto Stack
PUSH SS ---------- 16 Push SS Segment Selector onto Stack
PUSHA,PUSHAD ---------- 60 Push All to GPR Words or Doublewords
Redundant Grp1 ---------- 82 /2 Redundant encoding of group1 Eb,Ib opcodes
SALC ---------- D6 Set AL According to CF
Table B-3. Reassigned Instructions in 64-Bit Mode
ARPL ---------- 63 Opcode for MOVSXD instruction in 64-bit mode.
DEC and INC ---------- 40-4F REX prefixes in 64-bit mode.
B.3 Invalid and Reassigned Instructions in 64-Bit Mode
Table B-2 lists instructions that are illegal in 64-bit mode. Attempted use of these instructions
generates an invalid-opcode exception (#UD).
Table B-2. Invalid Instructions in 64-Bit Mode
AAA ---------- 37 ASCII Adjust After Addition
AAD ---------- D5 ASCII Adjust Before Division
AAM ---------- D4 ASCII Adjust After Multiply
AAS ---------- 3F ASCII Adjust After Subtraction
BOUND ---------- 62 Check Array Bounds
CALL (far) ---------- 9A Procedure Call Far (far absolute)
DAA ---------- 27 Decimal Adjust after Addition
DAS ---------- 2F Decimal Adjust after Subtraction
INTO ---------- CE Interrupt to Overflow Vector
JMP (far) ---------- EA Jump Far (absolute)
LDS ---------- C5 Load DS Far Pointer
LES ---------- C4 Load ES Far Pointer
POP DS ---------- 1F Pop Stack into DS Segment
POP ES ---------- 07 Pop Stack into ES Segment
POP SS ---------- 17 Pop Stack into SS Segment
POPA, POPAD ---------- 61 Pop All to GPR Words or Doublewords
PUSH CS ---------- 0E Push CS Segment Selector onto Stack
PUSH DS ---------- 1E Push DS Segment Selector onto Stack
PUSH ES ---------- 06 Push ES Segment Selector onto Stack
PUSH SS ---------- 16 Push SS Segment Selector onto Stack
PUSHA,PUSHAD ---------- 60 Push All to GPR Words or Doublewords
Redundant Grp1 ---------- 82 /2 Redundant encoding of group1 Eb,Ib opcodes
SALC ---------- D6 Set AL According to CF
Table B-3. Reassigned Instructions in 64-Bit Mode
ARPL ---------- 63 Opcode for MOVSXD instruction in 64-bit mode.
DEC and INC ---------- 40-4F REX prefixes in 64-bit mode.
I'm using AMD Sempron 140 Single core 2.7GHz