Paging issue with IDT

[iocoder]

Say I have 4 entries in GDT:
-> Entry for kernel CS 0x8.
-> Entry for kernel DS 0x10.
-> Entry for TSS of current task 0x18.
-> Entry for LDT of current task 0x20.
And there is 256 entries in IDT:
-> Each "used" entry has a logical address, with a selector value of "0x8" and an offset refers to the specific ISR.
And I have enabled Paging. Each task has its own Page Directory. During task switching, CR3 is changed to the new task's page directory base address.
My Question:
After changing the content of CR3 as said, an IRQ may invoke. when this IRQ invokes, the processor reads the logical address from the corresponding entry in kernel's IDT, doesn't it?, and then the logical address is translated using the page directory to which is referred by CR3, isn't it? so i have to make an IDT for each task, don't I?
Thanks and Regards, .

[b.zaar]

Generally you have one IDT which is mapped into every application. You usually map it somewhere in kernel memory which should also be mapped into every application. This is how a higher half kernel works